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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a6d0f10385sm9537215f8f.17.2025.06.23.05.19.52 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 23 Jun 2025 05:19:53 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Leif Lindholm , qemu-arm@nongnu.org, =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Roman Bolshakov , Paolo Bonzini , Alexander Graf , Bernhard Beschow , John Snow , Thomas Huth , =?utf-8?q?Mar?= =?utf-8?q?c-Andr=C3=A9_Lureau?= , kvm@vger.kernel.org, Eric Auger , Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Cameron Esfahani , Cleber Rosa , Radoslaw Biernacki , Phil Dennis-Jordan , Richard Henderson , =?utf-8?q?Alex_Benn=C3=A9?= =?utf-8?q?e?= Subject: [PATCH v3 13/26] target/arm: Create GTimers *after* features finalized / accel realized Date: Mon, 23 Jun 2025 14:18:32 +0200 Message-ID: <20250623121845.7214-14-philmd@linaro.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250623121845.7214-1-philmd@linaro.org> References: <20250623121845.7214-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Call generic (including accelerator) cpu_realize() handlers *before* setting @gt_cntfrq_hz default Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/cpu.c | 65 ++++++++++++++++++++++++------------------------ 1 file changed, 33 insertions(+), 32 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index e5b70f5de81..ab5fbd9b40b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1985,26 +1985,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) return; } - if (!cpu->gt_cntfrq_hz) { - /* - * 0 means "the board didn't set a value, use the default". (We also - * get here for the CONFIG_USER_ONLY case.) - * ARMv8.6 and later CPUs architecturally must use a 1GHz timer; before - * that it was an IMPDEF choice, and QEMU initially picked 62.5MHz, - * which gives a 16ns tick period. - * - * We will use the back-compat value: - * - for QEMU CPU types added before we standardized on 1GHz - * - for versioned machine types with a version of 9.0 or earlier - */ - if (arm_feature(env, ARM_FEATURE_BACKCOMPAT_CNTFRQ) || - cpu->backcompat_cntfrq) { - cpu->gt_cntfrq_hz = GTIMER_BACKCOMPAT_HZ; - } else { - cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ; - } - } - #ifndef CONFIG_USER_ONLY /* The NVIC and M-profile CPU are two halves of a single piece of * hardware; trying to use one without the other is a command line @@ -2051,7 +2031,40 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) return; } } +#endif + cpu_exec_realizefn(cs, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } + + arm_cpu_finalize_features(cpu, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } + +#ifndef CONFIG_USER_ONLY + if (!cpu->gt_cntfrq_hz) { + /* + * 0 means "the board didn't set a value, use the default". (We also + * get here for the CONFIG_USER_ONLY case.) + * ARMv8.6 and later CPUs architecturally must use a 1GHz timer; before + * that it was an IMPDEF choice, and QEMU initially picked 62.5MHz, + * which gives a 16ns tick period. + * + * We will use the back-compat value: + * - for QEMU CPU types added before we standardized on 1GHz + * - for versioned machine types with a version of 9.0 or earlier + */ + if (arm_feature(env, ARM_FEATURE_BACKCOMPAT_CNTFRQ) || + cpu->backcompat_cntfrq) { + cpu->gt_cntfrq_hz = GTIMER_BACKCOMPAT_HZ; + } else { + cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ; + } + } { uint64_t scale = gt_cntfrq_period_ns(cpu); @@ -2072,18 +2085,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) } #endif - cpu_exec_realizefn(cs, &local_err); - if (local_err != NULL) { - error_propagate(errp, local_err); - return; - } - - arm_cpu_finalize_features(cpu, &local_err); - if (local_err != NULL) { - error_propagate(errp, local_err); - return; - } - #ifdef CONFIG_USER_ONLY /* * User mode relies on IC IVAU instructions to catch modification of