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13 Oct 2020 17:28:42 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 3/4] hw/riscv: Add a riscv_is_32_bit() function Date: Tue, 13 Oct 2020 17:17:30 -0700 Message-Id: <4c6a85dfb6dd470aa79356ebc1b02f479c2758e0.1602634524.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=549b5cc2b=alistair.francis@wdc.com; helo=esa1.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/13 20:28:34 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Reviewed-by: Bin Meng Tested-by: Bin Meng --- include/hw/riscv/boot.h | 2 ++ hw/riscv/boot.c | 9 +++++++++ 2 files changed, 11 insertions(+) diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 0acbd8aa6e..2975ed1a31 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -23,6 +23,8 @@ #include "exec/cpu-defs.h" #include "hw/loader.h" +bool riscv_is_32_bit(MachineState *machine); + target_ulong riscv_find_and_load_firmware(MachineState *machine, const char *default_machine_firmware, hwaddr firmware_load_addr, diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index fa699308a0..5dea644f47 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -40,6 +40,15 @@ #define fw_dynamic_info_data(__val) cpu_to_le64(__val) #endif +bool riscv_is_32_bit(MachineState *machine) +{ + if (!strncmp(machine->cpu_type, "rv32", 4)) { + return true; + } else { + return false; + } +} + target_ulong riscv_find_and_load_firmware(MachineState *machine, const char *default_machine_firmware, hwaddr firmware_load_addr,