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envelope-from=prvs=558518344=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/23 11:44:34 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 6 ++--- target/riscv/cpu_helper.c | 52 ++++++++++++++++++++------------------- 2 files changed, 29 insertions(+), 29 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6096243aed..8bde15544d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -194,9 +194,8 @@ struct CPURISCVState { target_ulong vscause; target_ulong vstval; target_ulong vsatp; -#ifdef TARGET_RISCV32 + /* This is RV32 only */ target_ulong vsstatush; -#endif target_ulong mtval2; target_ulong mtinst; @@ -209,9 +208,8 @@ struct CPURISCVState { target_ulong stval_hs; target_ulong satp_hs; target_ulong mstatus_hs; -#ifdef TARGET_RISCV32 + /* This is RV32 only */ target_ulong mstatush_hs; -#endif target_ulong scounteren; target_ulong mcounteren; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 4652082df1..62aed24feb 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -126,10 +126,10 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) env->mstatus &= ~mstatus_mask; env->mstatus |= env->mstatus_hs; -#if defined(TARGET_RISCV32) - env->vsstatush = env->mstatush; - env->mstatush |= env->mstatush_hs; -#endif + if (riscv_cpu_is_32bit(env)) { + env->vsstatush = env->mstatush; + env->mstatush |= env->mstatush_hs; + } env->vstvec = env->stvec; env->stvec = env->stvec_hs; @@ -154,10 +154,10 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) env->mstatus &= ~mstatus_mask; env->mstatus |= env->vsstatus; -#if defined(TARGET_RISCV32) - env->mstatush_hs = env->mstatush; - env->mstatush |= env->vsstatush; -#endif + if (riscv_cpu_is_32bit(env)) { + env->mstatush_hs = env->mstatush; + env->mstatush |= env->vsstatush; + } env->stvec_hs = env->stvec; env->stvec = env->vstvec; @@ -472,11 +472,13 @@ restart: return TRANSLATE_PMP_FAIL; } -#if defined(TARGET_RISCV32) - target_ulong pte = address_space_ldl(cs->as, pte_addr, attrs, &res); -#elif defined(TARGET_RISCV64) - target_ulong pte = address_space_ldq(cs->as, pte_addr, attrs, &res); -#endif + target_ulong pte; + if (riscv_cpu_is_32bit(env)) { + pte = address_space_ldl(cs->as, pte_addr, attrs, &res); + } else { + pte = address_space_ldq(cs->as, pte_addr, attrs, &res); + } + if (res != MEMTX_OK) { return TRANSLATE_FAIL; } @@ -995,19 +997,19 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (riscv_cpu_virt_enabled(env)) { riscv_cpu_swap_hypervisor_regs(env); } -#ifdef TARGET_RISCV32 - env->mstatush = set_field(env->mstatush, MSTATUS_MPV, - riscv_cpu_virt_enabled(env)); - if (riscv_cpu_virt_enabled(env) && tval) { - env->mstatush = set_field(env->mstatush, MSTATUS_GVA, 1); - } -#else - env->mstatus = set_field(env->mstatus, MSTATUS_MPV, - riscv_cpu_virt_enabled(env)); - if (riscv_cpu_virt_enabled(env) && tval) { - env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1); + if (riscv_cpu_is_32bit(env)) { + env->mstatush = set_field(env->mstatush, MSTATUS_MPV, + riscv_cpu_virt_enabled(env)); + if (riscv_cpu_virt_enabled(env) && tval) { + env->mstatush = set_field(env->mstatush, MSTATUS_GVA, 1); + } + } else { + env->mstatus = set_field(env->mstatus, MSTATUS_MPV, + riscv_cpu_virt_enabled(env)); + if (riscv_cpu_virt_enabled(env) && tval) { + env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1); + } } -#endif mtval2 = env->guest_phys_fault_addr;