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23 Oct 2020 08:44:50 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 06/16] hw/riscv: spike: Remove compile time XLEN checks Date: Fri, 23 Oct 2020 08:33:29 -0700 Message-Id: <82ea05de42d429e1bf572cc134d4571d87a4cfc7.1603467169.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: References: MIME-Version: 1.0 Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=558518344=alistair.francis@wdc.com; helo=esa2.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/23 11:44:50 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- hw/riscv/spike.c | 45 ++++++++++++++++++++++++--------------------- 1 file changed, 24 insertions(+), 21 deletions(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 875f371f0f..3e47e4579d 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -43,17 +43,6 @@ #include "sysemu/qtest.h" #include "sysemu/sysemu.h" -/* - * Not like other RISC-V machines that use plain binary bios images, - * keeping ELF files here was intentional because BIN files don't work - * for the Spike machine as HTIF emulation depends on ELF parsing. - */ -#if defined(TARGET_RISCV32) -# define BIOS_FILENAME "opensbi-riscv32-generic-fw_dynamic.elf" -#else -# define BIOS_FILENAME "opensbi-riscv64-generic-fw_dynamic.elf" -#endif - static const struct MemmapEntry { hwaddr base; hwaddr size; @@ -64,7 +53,7 @@ static const struct MemmapEntry { }; static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap, - uint64_t mem_size, const char *cmdline) + uint64_t mem_size, const char *cmdline, bool is_32_bit) { void *fdt; uint64_t addr, size; @@ -115,11 +104,11 @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap, cpu_name = g_strdup_printf("/cpus/cpu@%d", s->soc[socket].hartid_base + cpu); qemu_fdt_add_subnode(fdt, cpu_name); -#if defined(TARGET_RISCV32) - qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32"); -#else - qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48"); -#endif + if (is_32_bit) { + qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32"); + } else { + qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48"); + } name = riscv_isa_string(&s->soc[socket].harts[cpu]); qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name); g_free(name); @@ -254,7 +243,8 @@ static void spike_board_init(MachineState *machine) main_mem); /* create device tree */ - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); + create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, + riscv_is_32_bit(machine)); /* boot rom */ memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom", @@ -262,9 +252,22 @@ static void spike_board_init(MachineState *machine) memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, mask_rom); - firmware_end_addr = riscv_find_and_load_firmware(machine, BIOS_FILENAME, - memmap[SPIKE_DRAM].base, - htif_symbol_callback); + /* + * Not like other RISC-V machines that use plain binary bios images, + * keeping ELF files here was intentional because BIN files don't work + * for the Spike machine as HTIF emulation depends on ELF parsing. + */ + if (riscv_is_32_bit(machine)) { + firmware_end_addr = riscv_find_and_load_firmware(machine, + "opensbi-riscv32-generic-fw_dynamic.elf", + memmap[SPIKE_DRAM].base, + htif_symbol_callback); + } else { + firmware_end_addr = riscv_find_and_load_firmware(machine, + "opensbi-riscv64-generic-fw_dynamic.elf", + memmap[SPIKE_DRAM].base, + htif_symbol_callback); + } if (machine->kernel_filename) { kernel_start_addr = riscv_calc_kernel_start_addr(machine,