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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id 43si1703813qgu.42.2014.05.29.09.48.06 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 29 May 2014 09:48:06 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:49219 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wq3Us-0005In-8g for patch@linaro.org; Thu, 29 May 2014 12:48:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48135) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wq3UE-0004tB-HT for qemu-devel@nongnu.org; Thu, 29 May 2014 12:47:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wq3U8-0003wA-F7 for qemu-devel@nongnu.org; Thu, 29 May 2014 12:47:26 -0400 Received: from mail-lb0-f179.google.com ([209.85.217.179]:64392) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wq3U8-0003vA-1k for qemu-devel@nongnu.org; Thu, 29 May 2014 12:47:20 -0400 Received: by mail-lb0-f179.google.com with SMTP id c11so351224lbj.10 for ; Thu, 29 May 2014 09:47:19 -0700 (PDT) X-Received: by 10.152.203.236 with SMTP id kt12mr7174189lac.8.1401382039084; Thu, 29 May 2014 09:47:19 -0700 (PDT) MIME-Version: 1.0 Received: by 10.112.158.228 with HTTP; Thu, 29 May 2014 09:46:59 -0700 (PDT) In-Reply-To: <1395764877-10487-1-git-send-email-ard.biesheuvel@linaro.org> References: <1395764877-10487-1-git-send-email-ard.biesheuvel@linaro.org> From: Peter Maydell Date: Thu, 29 May 2014 17:46:59 +0100 Message-ID: To: Ard Biesheuvel X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.217.179 Cc: QEMU Developers , Christoffer Dall Subject: Re: [Qemu-devel] [PATCH] target-arm: add support for v8 SHA1 and SHA256 instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.172 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 On 25 March 2014 16:27, Ard Biesheuvel wrote: > This adds support for the SHA1 and SHA256 instructions that are available > on some v8 implementations of Aarch32. > > Signed-off-by: Ard Biesheuvel Apologies for the incredibly late review; I was hugely busy back in March and then this slipped through the cracks and I forgot I needed to review it. I have a few nits below, but nothing major. I've tested this patch (comparison vs hardware) and apart from the missing UNDEF for Q!=1 check I mention below it is good. At the bottom of my review comments I've put the diff which I'm planning to squash into this patch; I'll send out that as a v2 of this patch, to save you doing the rebase and minor fixes yourself. > + } else { > + int i; > + > + for (i = 0; i < 4; i++) { > + uint32_t t; Bad indent. > + > + switch (op) { > + default: > + /* not reached */ g_assert_not_reached(); > @@ -4955,6 +4961,46 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins > if (q && ((rd | rn | rm) & 1)) { > return 1; > } > + /* > + * The SHA-1/SHA-256 3-register instructions require special treatment > + * here, as their size field is overloaded as an op type selector, and > + * they all consume their input in a single pass. > + */ > + if (op == NEON_3R_SHA) { Missing UNDEF case: if (!q) { return 1; } > + case NEON_2RM_SHA1SU1: > + if ((rm | rd) & 1) { > + return 1; > + } > + /* bit 6: set -> SHA256SU0, cleared -> SHA1SU1 */ > + if (extract32(insn, 6, 1)) { This is 'q', you don't need to re-extract it. Otherwise Reviewed-by: Peter Maydell Below is the diff I'm going to squash into this patch: return 1; @@ -6548,8 +6551,8 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins if ((rm | rd) & 1) { return 1; } - /* bit 6: set -> SHA256SU0, cleared -> SHA1SU1 */ - if (extract32(insn, 6, 1)) { + /* bit 6 (q): set -> SHA256SU0, cleared -> SHA1SU1 */ + if (q) { if (!arm_feature(env, ARM_FEATURE_V8_SHA256)) { return 1; } @@ -6558,7 +6561,7 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins } tmp = tcg_const_i32(rd); tmp2 = tcg_const_i32(rm); - if (extract32(insn, 6, 1)) { + if (q) { gen_helper_crypto_sha256su0(cpu_env, tmp, tmp2); } else { gen_helper_crypto_sha1su1(cpu_env, tmp, tmp2); thanks -- PMM diff --git a/target-arm/crypto_helper.c b/target-arm/crypto_helper.c index 4619dde..3e4b5f7 100644 --- a/target-arm/crypto_helper.c +++ b/target-arm/crypto_helper.c @@ -322,28 +322,28 @@ void HELPER(crypto_sha1_3reg)(CPUARMState *env, uint32_t rd, uint32_t rn, int i; for (i = 0; i < 4; i++) { - uint32_t t; - - switch (op) { - default: - /* not reached */ - case 0: /* sha1c */ - t = cho(d.words[1], d.words[2], d.words[3]); - break; - case 1: /* sha1p */ - t = par(d.words[1], d.words[2], d.words[3]); - break; - case 2: /* sha1m */ - t = maj(d.words[1], d.words[2], d.words[3]); - break; - } - t += rol32(d.words[0], 5) + n.words[0] + m.words[i]; - - n.words[0] = d.words[3]; - d.words[3] = d.words[2]; - d.words[2] = ror32(d.words[1], 2); - d.words[1] = d.words[0]; - d.words[0] = t; + uint32_t t; + + switch (op) { + case 0: /* sha1c */ + t = cho(d.words[1], d.words[2], d.words[3]); + break; + case 1: /* sha1p */ + t = par(d.words[1], d.words[2], d.words[3]); + break; + case 2: /* sha1m */ + t = maj(d.words[1], d.words[2], d.words[3]); + break; + default: + g_assert_not_reached(); + } + t += rol32(d.words[0], 5) + n.words[0] + m.words[i]; + + n.words[0] = d.words[3]; + d.words[3] = d.words[2]; + d.words[2] = ror32(d.words[1], 2); + d.words[1] = d.words[0]; + d.words[0] = t; } } env->vfp.regs[rd] = make_float64(d.l[0]); diff --git a/target-arm/translate.c b/target-arm/translate.c index d5ee7a1..ab3713d 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -5022,6 +5022,9 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins * they all consume their input in a single pass. */ if (op == NEON_3R_SHA) { + if (!q) { + return 1; + } if (!u) { /* SHA-1 */ if (!arm_feature(env, ARM_FEATURE_V8_SHA1)) {