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[209.132.180.67]) by mx.google.com with ESMTP id 102si8959663pld.125.2017.06.26.01.01.44; Mon, 26 Jun 2017 01:01:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=MX0J6Gog; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751388AbdFZIBo (ORCPT + 6 others); Mon, 26 Jun 2017 04:01:44 -0400 Received: from mail-pg0-f46.google.com ([74.125.83.46]:34284 "EHLO mail-pg0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751353AbdFZIBn (ORCPT ); Mon, 26 Jun 2017 04:01:43 -0400 Received: by mail-pg0-f46.google.com with SMTP id t186so5465384pgb.1 for ; Mon, 26 Jun 2017 01:01:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pFE+mO75YvwPDmvbpPM+vYBOvHEDngDYvXgHkBRkeg8=; b=MX0J6GogoprVkII6R6GDUV94OKDVZaZibVvndDhQ+Yo4M6GmggM689hr36BTmlfXPt PazKdbaGvV1zdtOMuALtOxnlG8RvWlLJ+v7YI+R4DgN5hisHNppORHLtwxgQLIiShWSy nj985pK1VgXJdlZhcwLqYAkMpbeZVs6bHJWDs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pFE+mO75YvwPDmvbpPM+vYBOvHEDngDYvXgHkBRkeg8=; b=sOeaZVK4KcRCUg3DbGNwsiVJWXmPcq0pYLT1WkK2h8jiH7NwLDI+0WixYW03gcysaM K3puX+EWeOV9TjE4sUCRWOEDQAlew7wXgy2G3NohQ4ST7HvcwavLW2vQxG6bPK9AzC25 Tggw7PyOeG9DkwdtwdcdxA3Q4rXPRSF1NK6y2OWG5C6t/KGN2oLx5n8BfO693Y7U+rEU TCeRusGhq37J7Pr1YEBi7UBOMjD8wsza+wJkDzHPOiNFOSgySaGSpaZlpnfyegYtssFK 73fe3quOs3/V8fDtAMNPv/ixP/J3SnetJHKV68ahsK2p+GHeqTUpp4+kfgql5Ox4Q1M9 gCVg== X-Gm-Message-State: AKS2vOwoRxA7OWontFP7xYciwj3cuYHm5rmsOocj3q2t3tdJk0800MOf Na1O4xF8SkGjysfA X-Received: by 10.84.218.71 with SMTP id f7mr22075044plm.282.1498464102685; Mon, 26 Jun 2017 01:01:42 -0700 (PDT) Received: from localhost.localdomain ([106.51.139.251]) by smtp.gmail.com with ESMTPSA id 67sm23673640pfa.83.2017.06.26.01.01.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 26 Jun 2017 01:01:41 -0700 (PDT) From: Amit Pundir To: Greg KH Cc: Stable , =?utf-8?q?Jo=C3=ABl_Esponde?= , Cyrille Pitchen Subject: [PATCH for-4.9 2/7] mtd: spi-nor: fix spansion quad enable Date: Mon, 26 Jun 2017 13:31:26 +0530 Message-Id: <1498464091-26753-3-git-send-email-amit.pundir@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1498464091-26753-1-git-send-email-amit.pundir@linaro.org> References: <1498464091-26753-1-git-send-email-amit.pundir@linaro.org> MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Joël Esponde commit 807c16253319ee6ccf8873ae64f070f7eb532cd5 upstream. With the S25FL127S nor flash part, each writing to the configuration register takes hundreds of ms. During that time, no more accesses to the flash should be done (even reads). This commit adds a wait loop after the register writing until the flash finishes its work. This issue could make rootfs mounting fail when the latter was done too much closely to this quad enable bit setting step. And in this case, a driver as UBIFS may try to recover the filesystem and may broke it completely. Signed-off-by: Joël Esponde Signed-off-by: Cyrille Pitchen Signed-off-by: Amit Pundir --- drivers/mtd/spi-nor/spi-nor.c | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.7.4 diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index d0fc165d7d66..21dde5249085 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1255,6 +1255,13 @@ static int spansion_quad_enable(struct spi_nor *nor) return -EINVAL; } + ret = spi_nor_wait_till_ready(nor); + if (ret) { + dev_err(nor->dev, + "timeout while writing configuration register\n"); + return ret; + } + /* read back and check it */ ret = read_cr(nor); if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {