From patchwork Wed Aug 30 05:06:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 111266 Delivered-To: patch@linaro.org Received: by 10.140.95.112 with SMTP id h103csp381825qge; Tue, 29 Aug 2017 22:06:38 -0700 (PDT) X-Received: by 10.99.111.6 with SMTP id k6mr399710pgc.138.1504069598103; Tue, 29 Aug 2017 22:06:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504069598; cv=none; d=google.com; s=arc-20160816; b=eoEO+7WE8LaN48lEdUeE5LhpkiimwrMFlDmHi9ZurUS9IXOxzzFiem5W0wbeYlWxHn nUPjbtL/RjQgy7lkUGqbYs58CaL1CHgaQ5OQavBC4p9Q/Pv/+HzXxO2VvVVeBXWvTsVk MCTG60W57pro3XoC3CVX/FvHU4U0XRbsxSMOGhwbbYWnnmz90/BJYykdGPV2o+kuR+GS rj5AqSa92oE9BnMAkq8MgNUFNtTdNJwr0ndvp9piTZG/VVfEpKmz426r50nlz8A2/IfG BCleNhu22iDcOU+C7ZkNdeWRPjqkAc5CeWKYzyGqPVDrg2x1u73OEOR+0MhqKvIHJ2KT v1hA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=fGhi4rEa83RPZehZP3kB7JD7xZN43I6ylmKVMa69vg0=; b=b9D2gzMlydB88bjTw1Xgiv9NKIoVu1pWjIKV97uvyOPqDcxSHHfLSsKT8MtYEKWuGu +ZxDJ6YSn3u0e/Lg2L+Oy2OJP/sD4AXTGWThosiTQHuDXABNDbv8/jZ/2PzFrmw+ffxl vYsZ/+1zq9Bo7d+McOwsHbnndx8Z0daLaTqY1rcByQj8oqWZOJEhkSjLa6mUyWe5C/xi 2Jm41iNB3J5yJHC/Dc6YabzF0ZQpvXtiCr1Dib52EDstRkZpHFkdk4791phJAshsoBSZ aMlrk3wQHQ8DzWkN0gNSvmbOT3JsfoI2PqmGVkV4Q2punnF+E+5dm0TrDDD3WThjo15a F3kw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YfQhbgKL; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f62si3549221pfb.472.2017.08.29.22.06.37; Tue, 29 Aug 2017 22:06:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YfQhbgKL; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750756AbdH3FGh (ORCPT + 6 others); Wed, 30 Aug 2017 01:06:37 -0400 Received: from mail-wm0-f50.google.com ([74.125.82.50]:34883 "EHLO mail-wm0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750743AbdH3FGg (ORCPT ); Wed, 30 Aug 2017 01:06:36 -0400 Received: by mail-wm0-f50.google.com with SMTP id a80so2842225wma.0 for ; Tue, 29 Aug 2017 22:06:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=fGhi4rEa83RPZehZP3kB7JD7xZN43I6ylmKVMa69vg0=; b=YfQhbgKLWATQBJWp8mPBsfa8oEcbx7BkOgRgy/+dvWX2QyAND7TcC1DjmClDgBD7io 0YBxrft11kT3aUIGvvJBe6eKu7LlpOE5N00sszLtW5nL2jONNFJ/d2y+OZ3g2Amgd19G xjeUrInMwyj1Jkx/XCVxVdZ+oE93lDLLnTQE0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=fGhi4rEa83RPZehZP3kB7JD7xZN43I6ylmKVMa69vg0=; b=N71PTkm3jOBZw9J21G8z38COXMIWc4m8KC7bp+6g7JtGmY8DDql7sTqJCVC+vlCN7A GWmGfp8GYXmAT0j322BDDM6ykMXG/8uGtfH2vafm8fUE8zkFTbpJpuDZSVXJBfeQXYZn lQL+y+2QiiG9Bz26Bqly+vxlGK+/B758kx6w6Ss6tInGwuZ5Dn9hEgcjoDsR/bSy5QjM Ha6YoY6ufUtLqhFxGt8u3SAWLR5aRqy3S9Hf/pZJt6vTRAePge9lUOKNpEzjJEX79P63 fLwJI2nofLNwHf6wGkMFSiiXbzlsC2nJ5nSpFC6D9McrgbEgZULSftvlKrLmFOrBUGhw ceRw== X-Gm-Message-State: AHYfb5jSQmQO9KOWtoBL+Koo9a7v6DlgkSE95kRlsKFBd/cg+o+Fg5CN G1ASEYATCixC+jfmD11KmA== X-Received: by 10.80.186.139 with SMTP id x11mr629705ede.260.1504069595360; Tue, 29 Aug 2017 22:06:35 -0700 (PDT) Received: from localhost.localdomain (li524-22.members.linode.com. [176.58.122.22]) by smtp.gmail.com with ESMTPSA id a13sm2676917edk.73.2017.08.29.22.06.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 29 Aug 2017 22:06:34 -0700 (PDT) From: Leo Yan To: stable@vger.kernel.org, Greg Kroah-Hartman , Marc Zyngier , John Stultz , Dmitry Shmidt Cc: Leo Yan Subject: [RESEND PATCH] arm64: arch_timer: Workaround for Cortex-A73 erratum 858921 Date: Wed, 30 Aug 2017 13:06:09 +0800 Message-Id: <1504069569-27809-1-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 2.7.4 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org commit fa8d815fac96e7c9247783d5a1f8fa4685b3c543 upstream. Cortex-A73 (all versions) counter read can return a wrong value when the counter crosses a 32bit boundary. The workaround involves performing the read twice, and to return one or the other depending on whether a transition has taken place. Signed-off-by: Marc Zyngier Signed-off-by: Leo Yan --- arch/arm64/Kconfig | 12 ++++++++++++ arch/arm64/include/asm/arch_timer.h | 11 +++++++++++ 2 files changed, 23 insertions(+) -- 2.7.4 diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 14cdc6d..68e7c98 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -374,6 +374,18 @@ config ARM64_ERRATUM_843419 If unsure, say Y. +config ARM64_ERRATUM_858921 + bool "Cortex-A73: 858921: arch timer counter read can return a wrong value" + default y + depends on ARM_ARCH_TIMER && ARM64 + help + This option enables a workaround applicable to Cortex-A73 + (all versions), whose counter may return incorrect values. + The workaround will be dynamically enabled when an affected + core is detected. + + If unsure, say Y. + config CAVIUM_ERRATUM_22375 bool "Cavium erratum 22375, 24313" default y diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h index fbe0ca3..9b2b0f5 100644 --- a/arch/arm64/include/asm/arch_timer.h +++ b/arch/arm64/include/asm/arch_timer.h @@ -114,6 +114,16 @@ static inline u64 arch_counter_get_cntpct(void) return 0; } +#ifdef CONFIG_ARM64_ERRATUM_858921 +static inline u64 arch_counter_get_cntvct(void) +{ + u64 old, new; + + asm volatile("mrs %0, cntvct_el0" : "=r" (old)); + asm volatile("mrs %0, cntvct_el0" : "=r" (new)); + return (((old ^ new) >> 32) & 1) ? old : new; +} +#else static inline u64 arch_counter_get_cntvct(void) { u64 cval; @@ -123,6 +133,7 @@ static inline u64 arch_counter_get_cntvct(void) return cval; } +#endif static inline int arch_timer_arch_init(void) {