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02 Dec 2017 15:53:09 +0000 Received: from tbwexch21apd.uswin.ad.vzwcorp.com (153.114.162.45) by OHTWI1EXH002.uswin.ad.vzwcorp.com (10.144.218.44) with Microsoft SMTP Server (TLS) id 14.3.248.2; Sat, 2 Dec 2017 10:53:09 -0500 Received: from OMZP1LUMXCA12.uswin.ad.vzwcorp.com (144.8.22.187) by tbwexch21apd.uswin.ad.vzwcorp.com (153.114.162.45) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Sat, 2 Dec 2017 10:53:08 -0500 Received: from OMZP1LUMXCA17.uswin.ad.vzwcorp.com (144.8.22.195) by OMZP1LUMXCA12.uswin.ad.vzwcorp.com (144.8.22.187) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Sat, 2 Dec 2017 09:53:07 -0600 Received: from OMZP1LUMXCA17.uswin.ad.vzwcorp.com ([144.8.22.195]) by OMZP1LUMXCA17.uswin.ad.vzwcorp.com ([144.8.22.195]) with mapi id 15.00.1263.000; Sat, 2 Dec 2017 09:53:07 -0600 To: "linux-kernel@vger.kernel.org" , "stable@vger.kernel.org" Subject: [PATCH AUTOSEL for 4.9 22/33] clk: uniphier: fix DAPLL2 clock rate of Pro5 Thread-Topic: [PATCH AUTOSEL for 4.9 22/33] clk: uniphier: fix DAPLL2 clock rate of Pro5 Thread-Index: AQHTa4WLBMba4kclrku6gwqVBNIulw== Date: Sat, 2 Dec 2017 15:52:24 +0000 Message-ID: <20171202155204.7691-22-alexander.levin@verizon.com> References: <20171202155204.7691-1-alexander.levin@verizon.com> In-Reply-To: <20171202155204.7691-1-alexander.levin@verizon.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-messagesentrepresentingtype: 1 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.144.60.250] MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Masahiro Yamada [ Upstream commit 67affb78a4e4feb837953e3434c8402a5c3b272f ] The parent of DAPLL2 should be DAPLL1. Fix the clock connection. Signed-off-by: Masahiro Yamada Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin --- drivers/clk/uniphier/clk-uniphier-sys.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.11.0 diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c index 5d029991047d..481225adef87 100644 --- a/drivers/clk/uniphier/clk-uniphier-sys.c +++ b/drivers/clk/uniphier/clk-uniphier-sys.c @@ -98,7 +98,7 @@ const struct uniphier_clk_data uniphier_sld8_sys_clk_data[] = { const struct uniphier_clk_data uniphier_pro5_sys_clk_data[] = { UNIPHIER_CLK_FACTOR("spll", -1, "ref", 120, 1), /* 2400 MHz */ UNIPHIER_CLK_FACTOR("dapll1", -1, "ref", 128, 1), /* 2560 MHz */ - UNIPHIER_CLK_FACTOR("dapll2", -1, "ref", 144, 125), /* 2949.12 MHz */ + UNIPHIER_CLK_FACTOR("dapll2", -1, "dapll1", 144, 125), /* 2949.12 MHz */ UNIPHIER_CLK_FACTOR("uart", 0, "dapll2", 1, 40), UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48), UNIPHIER_PRO5_SYS_CLK_SD,