[v4.9.y,21/27] arm64: cputype: Add MIDR values for Cavium ThunderX2 CPUs

From: Jayachandran C <jnair@caviumnetworks.com>

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From: Mark Rutland <mark.rutland@arm.com>
To: stable@vger.kernel.org
Cc: mark.brown@linaro.org, ard.biesheuvel@linaro.org,
	marc.zyngier@arm.com, will.deacon@arm.com
Subject: [PATCH v4.9.y 21/27] arm64: cputype: Add MIDR values for Cavium
	ThunderX2 CPUs
Date: Tue,  3 Apr 2018 12:09:17 +0100
Message-Id: <20180403110923.43575-22-mark.rutland@arm.com>
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References: <20180403110923.43575-1-mark.rutland@arm.com>
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Message ID	20180403110923.43575-22-mark.rutland@arm.com
State	New
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; From: Mark Rutland <mark.rutland@arm.com> To: stable@vger.kernel.org Cc: mark.brown@linaro.org, ard.biesheuvel@linaro.org, marc.zyngier@arm.com, will.deacon@arm.com Subject: [PATCH v4.9.y 21/27] arm64: cputype: Add MIDR values for Cavium ThunderX2 CPUs Date: Tue, 3 Apr 2018 12:09:17 +0100 Message-Id: <20180403110923.43575-22-mark.rutland@arm.com> In-Reply-To: <20180403110923.43575-1-mark.rutland@arm.com> References: <20180403110923.43575-1-mark.rutland@arm.com> Sender: stable-owner@vger.kernel.org Precedence: bulk
Series	arm64 meltdown patches \| expand [v4.9.y,00/27] arm64 meltdown patches [v4.9.y,01/27] arm64: mm: Use non-global mappings for kernel space [v4.9.y,02/27] arm64: mm: Move ASID from TTBR0 to TTBR1 [v4.9.y,03/27] arm64: mm: Allocate ASIDs in pairs [v4.9.y,04/27] arm64: mm: Add arm64_kernel_unmapped_at_el0 helper [v4.9.y,05/27] arm64: mm: Invalidate both kernel and user ASIDs when performing TLBI [v4.9.y,06/27] arm64: factor out entry stack manipulation [v4.9.y,07/27] module: extend 'rodata=off' boot cmdline parameter to module mappings [v4.9.y,08/27] arm64: entry: Add exception trampoline page for exceptions from EL0 [v4.9.y,09/27] arm64: mm: Map entry trampoline into trampoline and kernel page tables [v4.9.y,10/27] arm64: entry: Explicitly pass exception level to kernel_ventry macro [v4.9.y,11/27] arm64: entry: Hook up entry trampoline to exception vectors [v4.9.y,12/27] arm64: tls: Avoid unconditional zeroing of tpidrro_el0 for native tasks [v4.9.y,13/27] arm64: entry: Add fake CPU feature for unmapping the kernel at EL0 [v4.9.y,14/27] arm64: kaslr: Put kernel vectors address in separate data page [v4.9.y,15/27] arm64: use RET instruction for exiting the trampoline [v4.9.y,16/27] arm64: Kconfig: Add CONFIG_UNMAP_KERNEL_AT_EL0 [v4.9.y,17/27] arm64: Kconfig: Reword UNMAP_KERNEL_AT_EL0 kconfig entry [v4.9.y,18/27] arm64: Take into account ID_AA64PFR0_EL1.CSV3 [v4.9.y,19/27] arm64: Allow checking of a CPU-local erratum [v4.9.y,20/27] arm64: capabilities: Handle duplicate entries for a capability [v4.9.y,21/27] arm64: cputype: Add MIDR values for Cavium ThunderX2 CPUs [v4.9.y,22/27] arm64: Turn on KPTI only on CPUs that need it [v4.9.y,23/27] arm64: kpti: Make use of nG dependent on arm64_kernel_unmapped_at_el0() [v4.9.y,24/27] arm64: kpti: Add ->enable callback to remap swapper using nG mappings [v4.9.y,25/27] arm64: Force KPTI to be disabled on Cavium ThunderX [v4.9.y,26/27] arm64: entry: Reword comment about post_ttbr_update_workaround [v4.9.y,27/27] arm64: idmap: Use "awx" flags for .idmap.text .pushsection directives

[v4.9.y,21/27] arm64: cputype: Add MIDR values for Cavium ThunderX2 CPUs

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Patch