From patchwork Thu Apr 12 11:11:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 133211 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp1571780ljb; Thu, 12 Apr 2018 04:12:47 -0700 (PDT) X-Google-Smtp-Source: AIpwx4+lrSUtBa3LqsbL6Lny62xg6s032EwXUANhkZVVk64tRJ5iTpMmQjjOsALtkJ6UFeJPQRu2 X-Received: by 2002:a17:902:5902:: with SMTP id o2-v6mr539394pli.81.1523531567108; Thu, 12 Apr 2018 04:12:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1523531567; cv=none; d=google.com; s=arc-20160816; b=f9KQWQExgX5Fi9H9rHXA6InGm9y7cKxGzrQpWAZg9bWtQ9nOsjAYwRqfZKcwe+vbRl qMTlfkhdj0spHj5DyNGxR0BOVUPUuwuzfCFIa3cM5rf5Xg9uw4iIujFljpHDDwNeHntB z7SV9CdZArSyTKYAqHPuYLzgnCofLLWrlNXD6X+s3/aAQbNsgqqyzNzBGxo0kY87Sbz7 AG5d++61EZU/3AjONQIeq2yFTKE8A83RxYql96mRHOwrpBnKmIgdIExJFh4hG8RDR3wy 53f8On6a6+tPpCEJXbbj36KyfFFGlcLkF/kL78vI7q3wnOt/zD8LJ7QxueKKhBp/+z0x ABxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=jscamO5Ibg8ykHN3bu2obkaxvIaleWCcFTZGcSiGFqk=; b=J5MsQIVBejrLe2bBzak3X62pA+090PGT4COS7smrFa13lNLSLRE5tqz5lzN1+TQaNF ADe8Q04tqz8LD7onWwEL0I5kX9+s6RMRBh33XK4pGPRXLjF/0MMAZW9+fQlhh4gUxbCu 3WYVr5pv8dMaHLmONz2Ss40r5UbvxMZqsBUz1N1IlaPPkABzQ831p9b7ptY49V4WepCo k6/miiPYkML408q7Jqks36nc2oGjlRVsrqGDRD8YLkg971gKQYBSYFmPsCvzli8gfY5d uTdjszC+eSMPo3XEsZnrydYlcK0+znXAm1uGb4BQ2iAgpqcPpN6OP2MVj+0XJ7tYnVj9 8juQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id bg3-v6si3001807plb.118.2018.04.12.04.12.46; Thu, 12 Apr 2018 04:12:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752870AbeDLLMq (ORCPT + 11 others); Thu, 12 Apr 2018 07:12:46 -0400 Received: from foss.arm.com ([217.140.101.70]:59446 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752866AbeDLLMp (ORCPT ); Thu, 12 Apr 2018 07:12:45 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 742F180D; Thu, 12 Apr 2018 04:12:45 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C92FD3F24A; Thu, 12 Apr 2018 04:12:43 -0700 (PDT) From: Mark Rutland To: stable@vger.kernel.org Cc: mark.brown@linaro.org, ard.biesheuvel@linaro.org, marc.zyngier@arm.com, will.deacon@arm.com, catalin.marinas@arm.com, ghackmann@google.com, shankerd@codeaurora.org Subject: [PATCH v4.9.y 16/42] arm64: Move post_ttbr_update_workaround to C code Date: Thu, 12 Apr 2018 12:11:12 +0100 Message-Id: <20180412111138.40990-17-mark.rutland@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180412111138.40990-1-mark.rutland@arm.com> References: <20180412111138.40990-1-mark.rutland@arm.com> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marc Zyngier commit 95e3de3590e3f2358bb13f013911bc1bfa5d3f53 upstream. We will soon need to invoke a CPU-specific function pointer after changing page tables, so move post_ttbr_update_workaround out into C code to make this possible. Signed-off-by: Marc Zyngier Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Mark Rutland [v4.9 backport] --- arch/arm64/include/asm/assembler.h | 13 ------------- arch/arm64/mm/context.c | 9 +++++++++ arch/arm64/mm/proc.S | 3 +-- 3 files changed, 10 insertions(+), 15 deletions(-) -- 2.11.0 diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index c9bd4ad4db82..e60375ce0dd2 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -435,17 +435,4 @@ alternative_endif and \phys, \pte, #(((1 << (48 - PAGE_SHIFT)) - 1) << PAGE_SHIFT) .endm -/* - * Errata workaround post TTBR0_EL1 update. - */ - .macro post_ttbr0_update_workaround -#ifdef CONFIG_CAVIUM_ERRATUM_27456 -alternative_if ARM64_WORKAROUND_CAVIUM_27456 - ic iallu - dsb nsh - isb -alternative_else_nop_endif -#endif - .endm - #endif /* __ASM_ASSEMBLER_H */ diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index f00f5eeb556f..b9b087564bac 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -233,6 +233,15 @@ void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) cpu_switch_mm(mm->pgd, mm); } +/* Errata workaround post TTBRx_EL1 update. */ +asmlinkage void post_ttbr_update_workaround(void) +{ + asm(ALTERNATIVE("nop; nop; nop", + "ic iallu; dsb nsh; isb", + ARM64_WORKAROUND_CAVIUM_27456, + CONFIG_CAVIUM_ERRATUM_27456)); +} + static int asids_init(void) { asid_bits = get_cpu_asid_bits(); diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 135a698ce946..619da1cbd32b 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -139,8 +139,7 @@ ENTRY(cpu_do_switch_mm) isb msr ttbr0_el1, x0 // now update TTBR0 isb - post_ttbr0_update_workaround - ret + b post_ttbr_update_workaround // Back to C code... ENDPROC(cpu_do_switch_mm) .pushsection ".idmap.text", "awx"