From patchwork Fri Mar 22 16:17:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 160941 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp993809jan; Fri, 22 Mar 2019 09:18:11 -0700 (PDT) X-Google-Smtp-Source: APXvYqzM/mV8YP6EPNtKBs3E3xBiP4BAUivkdFLmX7dVzxLYK7xrFbd8ogKptlHaepDL27qhd1e7 X-Received: by 2002:a62:1795:: with SMTP id 143mr6499046pfx.104.1553271491901; Fri, 22 Mar 2019 09:18:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553271491; cv=none; d=google.com; s=arc-20160816; b=UE8QtZw9EFqMbjFiq25LYQfzNDzXwjBU1GKnWgIRIywPSOCYDrf/CcgELKlmbGK54p AifohAPeuL0ugiy393W7EZzzUaAJ+gS8JZyKwrJs+YdxyflOK/hUkJDvKn1xb0Q5sRhf eCiCfEwN/8K6HaQLkSznDyLrYxcvG/Am3Eonw36fuF6f/Q2uzhAVnxBd3apBmCdvDFx4 /umlcw6x0lP5kCDB1UHiUYqZLtUEnWZth6cbGBHKRfk1w5aR3spdD8cP/T590uTYHDdi PT+aMxqz9nvLAIWKZv+YzaBYtTaqyK78mWVxNuB9+Zph0GMm2Fso+FQR/wBUs/i1N0Wk G+ow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=s0swqgxhNosK4SHheS4iVEc3at5oxdvVYMmQjYT2XSI=; b=PfounTN+yrUTie1pC6a42xyJxLteVkU3/hCP5ez6pTOXJkhJJUDyDhGMhlb+6da/+1 +48KcSAQgUwtOKGe88gKjcMvgbg22oBOaEG1ekCjY/F7pEO3tLgsYSRWnVpjzZG/FMyH hYLKLwd2CSa6a5b5mFqstJsMWMNJkiWqiwQzxnkrvLrJYhwJgCjSC+3EDZyZi8G7OFrM b8VUDsuF3BgGtZsuSC3rIDTK0Q9RKCpko6ODZl/Wt3yeFSkiEh/kC5im+2LCG7JUhkCZ LJEJ8ZCKyqBR4StN1okeyVFA1ybkAHWNxCQ8S7w0VyWgagk7aAps9ZUUYZgWXGP5EyNl /Xww== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u4si6838652pgh.278.2019.03.22.09.18.11; Fri, 22 Mar 2019 09:18:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727990AbfCVQSL (ORCPT + 14 others); Fri, 22 Mar 2019 12:18:11 -0400 Received: from mout.kundenserver.de ([217.72.192.74]:56887 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727887AbfCVQSL (ORCPT ); Fri, 22 Mar 2019 12:18:11 -0400 Received: from wuerfel.lan ([149.172.19.189]) by mrelayeu.kundenserver.de (mreue108 [212.227.15.145]) with ESMTPA (Nemesis) id 1N4R0a-1gyGEE2KF4-011WD6; Fri, 22 Mar 2019 17:17:56 +0100 From: Arnd Bergmann To: stable@vger.kernel.org, Jingoo Han , Joao Pinto , Lorenzo Pieralisi , Bjorn Helgaas Cc: Niklas Cassel , Gustavo Pimentel , Joao Pinto , Arnd Bergmann , Sasha Levin , Kishon Vijay Abraham I , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [BACKPORT 4.14.y 3/8] PCI: designware-ep: Read-only registers need DBI_RO_WR_EN to be writable Date: Fri, 22 Mar 2019 17:17:18 +0100 Message-Id: <20190322161727.1153278-4-arnd@arndb.de> X-Mailer: git-send-email 2.20.0 In-Reply-To: <20190322161727.1153278-1-arnd@arndb.de> References: <20190322161727.1153278-1-arnd@arndb.de> MIME-Version: 1.0 X-Provags-ID: V03:K1:7BnjHSR4SGPL5O3iW2s2eF984rMLHtb/Z9rhiT9lkOTIb39GVI3 hQtWPoO/mMPxp17/3ZU82z1T0gk6EIgXpT8Zy2BF8MfaPrR1TZ2Mbvlu8DnLpsl7zUqfqc2 H1xvyjI3wl5D5wEr3IYLZZ1W+XCXF36k2ihAWilhu3CdEcwFbsJkvoiGL93/pWMYWDpUiOP s6dkhRXzQZObRFJI5EIGQ== X-Spam-Flag: NO X-UI-Out-Filterresults: notjunk:1; V03:K0:17/Qz6aOfMk=:6VHlA6OIxePe+TiHtj83Ik FWXxQ/0KmePvCCJvWxAFwgxUE1LNAftApU6ai9SuFoRv8Tipqb2gN6LWaXzW8w5lH25aN2JFK Uf7WRhcZmIXR3RDcHbnoD61UsoDFdAfktEysc4ZKB5At48SyOZN/PX116X8al8Hr0Ambsr93Q kxoKlMFq9HoT29vniSHyi+pTN6Zg6O2AviF3zOLltAVfOhj1xyk9goI1DwSmI/JqON8A170kt TN+quaZyEomexWQiF3+696YXt17jrgUflQeSKI8pH1OtgtbDDjpmxky54P4OoxXiXemtNBMoD d5p5BeFK6F8DhPWg/guSRJ/qarrqWxUteCYWR3RsVKKoQyWtW55LL9SICT6122/cjaV5+RTT/ 8uWm3Cs+nrXlHCY+jQnQWKvLvugpr66uxhf1XWa2Bwod2dRcjHouuRFXUXZtbrbBlF8qyAcmY IZNxZhlTuDjpnno9VEtgznT6fMvOTF7WNy2Wqjc9MkJJRjw7rqg5xKQ2pwR/nLomHP+Xsx8vx Qu4PKfRbIMBGMgYDcKp3y21X5T++7mMPRm+2AJBRg+aa9SbbyooiTdxRhtbAh1x7HmCRH3/51 Dy/xzPD5LJH9K9dVV48Pn6e9GFTrQa1kXg8J45LPzB9Plxw1MMPX/nHQL1PVzS/owr1cFVcuA xqpePZUamn/nm1pEXVIHjlK015udOe2jeNlJh3GdjvCRGC9En6ftcY8aecmcjsO48VdvuWW/t DBsGqZz7vV2F3jDAzqx+Z1IJko3pkavs4eTWng== Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Niklas Cassel Certain registers that pcie-designware-ep tries to write to are read-only registers. However, these registers can become read/write if we first enable the DBI_RO_WR_EN bit. Set/unset the DBI_RO_WR_EN bit before/after writing these registers. Tested-by: Gustavo Pimentel Signed-off-by: Niklas Cassel Signed-off-by: Lorenzo Pieralisi Acked-by: Joao Pinto (cherry picked from commit 1cab826b30c6275d479a6ab1dea1067e15dbec62) Signed-off-by: Arnd Bergmann --- drivers/pci/dwc/pcie-designware-ep.c | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.20.0 diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie-designware-ep.c index df317d390317..abcbf0770358 100644 --- a/drivers/pci/dwc/pcie-designware-ep.c +++ b/drivers/pci/dwc/pcie-designware-ep.c @@ -35,8 +35,10 @@ static void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar) u32 reg; reg = PCI_BASE_ADDRESS_0 + (4 * bar); + dw_pcie_dbi_ro_wr_en(pci); dw_pcie_writel_dbi2(pci, reg, 0x0); dw_pcie_writel_dbi(pci, reg, 0x0); + dw_pcie_dbi_ro_wr_dis(pci); } static int dw_pcie_ep_write_header(struct pci_epc *epc, @@ -45,6 +47,7 @@ static int dw_pcie_ep_write_header(struct pci_epc *epc, struct dw_pcie_ep *ep = epc_get_drvdata(epc); struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + dw_pcie_dbi_ro_wr_en(pci); dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, hdr->vendorid); dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, hdr->deviceid); dw_pcie_writeb_dbi(pci, PCI_REVISION_ID, hdr->revid); @@ -58,6 +61,7 @@ static int dw_pcie_ep_write_header(struct pci_epc *epc, dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_ID, hdr->subsys_id); dw_pcie_writeb_dbi(pci, PCI_INTERRUPT_PIN, hdr->interrupt_pin); + dw_pcie_dbi_ro_wr_dis(pci); return 0; } @@ -142,8 +146,10 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, enum pci_barno bar, if (ret) return ret; + dw_pcie_dbi_ro_wr_en(pci); dw_pcie_writel_dbi2(pci, reg, size - 1); dw_pcie_writel_dbi(pci, reg, flags); + dw_pcie_dbi_ro_wr_dis(pci); return 0; } @@ -217,7 +223,9 @@ static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 encode_int) val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL); val &= ~MSI_CAP_MMC_MASK; val |= (encode_int << MSI_CAP_MMC_SHIFT) & MSI_CAP_MMC_MASK; + dw_pcie_dbi_ro_wr_en(pci); dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val); + dw_pcie_dbi_ro_wr_dis(pci); return 0; }