From patchwork Tue Mar 17 10:55:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg KH X-Patchwork-Id: 229228 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10A77C2BB1D for ; Tue, 17 Mar 2020 11:18:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DAD2D20663 for ; Tue, 17 Mar 2020 11:18:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1584443938; bh=Q2KuvY2wUIITZZ23RE0KyIC+rdvVru0ndU38jehTFXk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=gpYNEFVlqU0K/mmfaEwG38jANpYQa14KeNOailazndHu4XtRbVoJKheH2ZX89+QZr xEmoD4fSkaeV2CI2zAcHSJpzcTyVTyoQsRgibTkl4k27ZLnoIkL894d8fa+3yaYWc6 lQfhNjBFbYOS8FkTe4NI4z8IiAPx6acyq+FStAmo= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726696AbgCQLSy (ORCPT ); Tue, 17 Mar 2020 07:18:54 -0400 Received: from mail.kernel.org ([198.145.29.99]:45896 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728375AbgCQLFK (ORCPT ); Tue, 17 Mar 2020 07:05:10 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 59B5D2073E; Tue, 17 Mar 2020 11:05:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1584443109; bh=Q2KuvY2wUIITZZ23RE0KyIC+rdvVru0ndU38jehTFXk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=W/sQoccfP8PKK0Fu1cJnrBdkqKbzGp5gvoDzIH7Ag9p3qJAXVueO1yGe+b2kKbKzz RlkkJex/19XkZD99f3uBOalzgm9gZfZskRBpLSzyVhRL9Ciwzt4M2xX3U7RjHbdPUh VW3oQZhNOj9fF01r0pgO1Hn1so9KUAJfDVrRm2ro= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Jerome Brunet , Nicolas Belin , Linus Walleij Subject: [PATCH 5.4 099/123] pinctrl: meson-gxl: fix GPIOX sdio pins Date: Tue, 17 Mar 2020 11:55:26 +0100 Message-Id: <20200317103317.809677515@linuxfoundation.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200317103307.343627747@linuxfoundation.org> References: <20200317103307.343627747@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Nicolas Belin commit dc7a06b0dbbafac8623c2b7657e61362f2f479a7 upstream. In the gxl driver, the sdio cmd and clk pins are inverted. It has not caused any issue so far because devices using these pins always take both pins so the resulting configuration is OK. Fixes: 0f15f500ff2c ("pinctrl: meson: Add GXL pinctrl definitions") Reviewed-by: Jerome Brunet Signed-off-by: Nicolas Belin Link: https://lore.kernel.org/r/1582204512-7582-1-git-send-email-nbelin@baylibre.com Signed-off-by: Linus Walleij Signed-off-by: Greg Kroah-Hartman --- drivers/pinctrl/meson/pinctrl-meson-gxl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) --- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c @@ -147,8 +147,8 @@ static const unsigned int sdio_d0_pins[] static const unsigned int sdio_d1_pins[] = { GPIOX_1 }; static const unsigned int sdio_d2_pins[] = { GPIOX_2 }; static const unsigned int sdio_d3_pins[] = { GPIOX_3 }; -static const unsigned int sdio_cmd_pins[] = { GPIOX_4 }; -static const unsigned int sdio_clk_pins[] = { GPIOX_5 }; +static const unsigned int sdio_clk_pins[] = { GPIOX_4 }; +static const unsigned int sdio_cmd_pins[] = { GPIOX_5 }; static const unsigned int sdio_irq_pins[] = { GPIOX_7 }; static const unsigned int nand_ce0_pins[] = { BOOT_8 };