From patchwork Tue Jun 23 19:55:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Kroah-Hartman X-Patchwork-Id: 191587 Delivered-To: patch@linaro.org Received: by 2002:a54:3249:0:0:0:0:0 with SMTP id g9csp1356696ecs; Tue, 23 Jun 2020 14:07:26 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwssbrPeSrC3kJtDD+lOY09NnPMLP+oMK1rxWauZSWgkqXB0YfmD3KaTmTcuN+EJfA7rtOd X-Received: by 2002:a17:906:191a:: with SMTP id a26mr12314357eje.315.1592946446867; Tue, 23 Jun 2020 14:07:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1592946446; cv=none; d=google.com; s=arc-20160816; b=qLqSXpGAkhq4zA0IFv/ReFSZf2mz2G/VbhvK13BE3KOJ0PPEDPuGcdha88M9vsn80i W/msbAJy61p+iN4X58NSwvNgDS6tuRGhv8DBVUclOUZTfMe6onEKuGcvog7L8sNMRTPC /aynOQsSzOojAXt/hIhcFwn4ghUl6hp35R2xs9RuTgzNUBjL9164CII+b/DLfmow/nUq YHmrczs30aim6BZPbN4FU45wsNrK6FnC38BSsmqY4j3BYNoiOrrvTEoUmVlyrw5d0M0H 6wogJTbjbv+IuvC2BpNaOSC0pM2VXTHbda4gNii/TGs3TM6RLPDHEokaG4bRq2w45xKt KOaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :user-agent:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=GTaii70ieJ0uDkJ+H+gl191m82hw+ctXy1cmpN0rP1c=; b=tDvc/TsRzisc7XqE5UQvTAXfn4ZuQX24VzQteRm6dxiGlOXTb1qXH/w0ABXsQcqyDm YXpCLVAA4CPHxVqD3n/EVC3tlrDEO0BCM8OGubv6josNw6g/RRdx9iuCrHNslQhD9WqM O5qXPTwkPD2MBYWrSC5pa7vIh/k8zc52NZQWLFvr8BBFsU/Glnz7iHmd1yFbGZ0Ih/yU wZ2OtvDy2durvTgzLd7Ne23DhA6sra5OqZvknw1DNEjQa2xEFIyNSyZ1GJtjGSL4s0Ia AY23AkH3zzm6/b8U9tnmbfluS75nuZzsv3nej+othiXBsBFEz0Tfj9db4xwd3KPPE/JX f9aQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=ICXw3SOU; spf=pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id v21si11809085edy.131.2020.06.23.14.07.26; Tue, 23 Jun 2020 14:07:26 -0700 (PDT) Received-SPF: pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=ICXw3SOU; spf=pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2393081AbgFWVH0 (ORCPT + 15 others); Tue, 23 Jun 2020 17:07:26 -0400 Received: from mail.kernel.org ([198.145.29.99]:57460 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391605AbgFWUfM (ORCPT ); Tue, 23 Jun 2020 16:35:12 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 438372064B; Tue, 23 Jun 2020 20:35:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1592944511; bh=OWznHjsmVWx26HdBIhqhwEMAILFno5xtuUsT/6PA4jM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ICXw3SOURGnd6vX/Updh3mP3OWTy/zDY45JBqO+IsIaknA5Mcil3wMwZsTQIWRkcv 4vHdnd3/AGoq8mKFYHj6tCDjJvzTb6qx67GagnkWy7BEfvXRbzo7PT8H3oWIwPq3on 3D5fKSPm8ygW50p7A3vocweOm0bIEf7J0FptafHw= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Marek Szyprowski , Chanwoo Choi , Sylwester Nawrocki , Sasha Levin Subject: [PATCH 4.19 019/206] clk: samsung: Mark top ISP and CAM clocks on Exynos542x as critical Date: Tue, 23 Jun 2020 21:55:47 +0200 Message-Id: <20200623195317.916537175@linuxfoundation.org> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200623195316.864547658@linuxfoundation.org> References: <20200623195316.864547658@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Marek Szyprowski [ Upstream commit e47bd937e602bb4379546095d1bd0b9871fa60c2 ] The TOP 'aclk*_isp', 'aclk550_cam', 'gscl_wa' and 'gscl_wb' clocks must be kept enabled all the time to allow proper access to power management control for the ISP and CAM power domains. The last two clocks, although related to GScaler device and GSCL power domain, provides also the I_WRAP_CLK signal to MIPI CSIS0/1 devices, which are a part of CAM power domain and are needed for proper power on/off sequence. Currently there are no drivers for the devices, which are part of CAM and ISP power domains yet. This patch only fixes the race between disabling the unused power domains and disabling unused clocks, which randomly resulted in the following error during boot: Power domain CAM disable failed Power domain ISP disable failed Fixes: 318fa46cc60d ("clk/samsung: exynos542x: mark some clocks as critical") Signed-off-by: Marek Szyprowski Acked-by: Chanwoo Choi Signed-off-by: Sylwester Nawrocki Signed-off-by: Sasha Levin --- drivers/clk/samsung/clk-exynos5420.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) -- 2.25.1 diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 6473af8903c58..662bb441f1392 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -597,7 +597,7 @@ static const struct samsung_div_clock exynos5800_div_clks[] __initconst = { static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = { GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam", - GATE_BUS_TOP, 24, 0, 0), + GATE_BUS_TOP, 24, CLK_IS_CRITICAL, 0), GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler", GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0), GATE(CLK_MAU_EPLL, "mau_epll", "mout_user_mau_epll", @@ -984,25 +984,25 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg", GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0), GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0", - GATE_BUS_TOP, 5, 0, 0), + GATE_BUS_TOP, 5, CLK_IS_CRITICAL, 0), GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl", GATE_BUS_TOP, 6, CLK_IS_CRITICAL, 0), GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl", GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0), GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp", - GATE_BUS_TOP, 8, 0, 0), + GATE_BUS_TOP, 8, CLK_IS_CRITICAL, 0), GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_pclk66_gpio", GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0), GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen", GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0), GATE(0, "aclk266_isp", "mout_user_aclk266_isp", - GATE_BUS_TOP, 13, 0, 0), + GATE_BUS_TOP, 13, CLK_IS_CRITICAL, 0), GATE(0, "aclk166", "mout_user_aclk166", GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0), GATE(CLK_ACLK333, "aclk333", "mout_user_aclk333", GATE_BUS_TOP, 15, CLK_IS_CRITICAL, 0), GATE(0, "aclk400_isp", "mout_user_aclk400_isp", - GATE_BUS_TOP, 16, 0, 0), + GATE_BUS_TOP, 16, CLK_IS_CRITICAL, 0), GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl", GATE_BUS_TOP, 17, CLK_IS_CRITICAL, 0), GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1", @@ -1208,8 +1208,10 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { GATE_IP_GSCL1, 3, 0, 0), GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333", GATE_IP_GSCL1, 4, 0, 0), - GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 0, 0), - GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 0, 0), + GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, + CLK_IS_CRITICAL, 0), + GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, + CLK_IS_CRITICAL, 0), GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333", GATE_IP_GSCL1, 16, 0, 0), GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",