From patchwork Wed Jul 1 23:17:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suzuki K Poulose X-Patchwork-Id: 192181 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp928721ilg; Wed, 1 Jul 2020 16:17:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxiXy6aMNxA8aqd7+P1cWRxQYAV59Rp3KNJ/mWrYBvIu4zjDiCI2Ygaf/FTuKrIXy9aqJ2m X-Received: by 2002:a50:fd12:: with SMTP id i18mr32525207eds.371.1593645438826; Wed, 01 Jul 2020 16:17:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1593645438; cv=none; d=google.com; s=arc-20160816; b=xJWJH/f602X1JdKAxojPzpI8TpucILhONDUFPkS5Y4wxHnODOhq/MNqQx6T/BqKirh x8FgiYTQEzBjrmcjbY5JsvQqs05MBK39Q3OdBA4N6FFCYUU8rStqFcvorx68MeoD61dx b6uPs1H5ePs3sRza+Qdd0r9+1r4YEVhfBBTVGK3K3ESB1V81sff9vUvkB05Myr0Z9wVI tGnpoGIyB9utOkyhEL2kX2YLhvimZoEDZ1VhulJXcojtyCKFmTToR2LX9o3B9qsYKG7v m5pUdHko9rJ6V6GPWqhhACEKbR1ioDh8E0QKFO8gwvwTVZ/32AQtEGlzKP3OMjULNkoe Zw/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=I+xOlqR5+Dw+kdpzK+3A3p/kKh/wZscvtFB5ALsuxdc=; b=xaKqzhCsnFPPrh0ubEKDtS5uEf/6WsjUl8IUkFYBa/cCGvM5CW4nS6bPM0RLQ3neOi F0VXnOwSVaWdYACtkpsmSnNavezvblWk1v7wUR5+4ZsB17qDG3j0ZLzP8/Dw52MhZKbU khJ3qC1G6PHSQfkplAkocL4URRmKQACwBO00e4ZxdAdrxMDtZx8ly2nHBeQkjhTpCwy/ nMFZc68NwIQYs8fktQ8RH3qGo4YeyrErHw5EtPAwr7knf0FlmD+htPh1ppaENEWdI6b4 GJM1IwAm7hbcIWx2ebAbL3IYtqSOrLnzmyLoc9p+1sigatyvUKYlkjBSKdolDu2raAIe 5xPA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id z14si5564696edl.500.2020.07.01.16.17.18; Wed, 01 Jul 2020 16:17:18 -0700 (PDT) Received-SPF: pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726366AbgGAXRR (ORCPT + 15 others); Wed, 1 Jul 2020 19:17:17 -0400 Received: from foss.arm.com ([217.140.110.172]:59200 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726312AbgGAXRR (ORCPT ); Wed, 1 Jul 2020 19:17:17 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4FB8631B; Wed, 1 Jul 2020 16:17:16 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.1.197.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 661783F73C; Wed, 1 Jul 2020 16:17:15 -0700 (PDT) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Cc: stable@vger.kernel.org, mathieu.poirier@linaro.org, coresight@lists.linaro.org, Suzuki K Poulose , Mike Leach Subject: [PATCH] coresight: etm4x: Fix save/restore during cpu idle Date: Thu, 2 Jul 2020 00:17:01 +0100 Message-Id: <20200701231701.91029-1-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.24.1 MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org The ETM state save/restore incorrectly reads/writes some of the 64bit registers (e.g, address comparators, vmid/cid comparators etc.) using 32bit accesses. Ensure we use the appropriate width accessors for the registers. Fixes: f188b5e76aae ("coresight: etm4x: Save/restore state across CPU low power states") Cc: Mathieu Poirier Cc: Mike Leach Signed-off-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-etm4x.c | 16 ++++++++-------- drivers/hwtracing/coresight/coresight-etm4x.h | 2 +- 2 files changed, 9 insertions(+), 9 deletions(-) -- 2.24.1 diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 82fc2fab072a..be990457a8ea 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -1206,8 +1206,8 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) } for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) { - state->trcacvr[i] = readl(drvdata->base + TRCACVRn(i)); - state->trcacatr[i] = readl(drvdata->base + TRCACATRn(i)); + state->trcacvr[i] = readq(drvdata->base + TRCACVRn(i)); + state->trcacatr[i] = readq(drvdata->base + TRCACATRn(i)); } /* @@ -1218,10 +1218,10 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) */ for (i = 0; i < drvdata->numcidc; i++) - state->trccidcvr[i] = readl(drvdata->base + TRCCIDCVRn(i)); + state->trccidcvr[i] = readq(drvdata->base + TRCCIDCVRn(i)); for (i = 0; i < drvdata->numvmidc; i++) - state->trcvmidcvr[i] = readl(drvdata->base + TRCVMIDCVRn(i)); + state->trcvmidcvr[i] = readq(drvdata->base + TRCVMIDCVRn(i)); state->trccidcctlr0 = readl(drvdata->base + TRCCIDCCTLR0); state->trccidcctlr1 = readl(drvdata->base + TRCCIDCCTLR1); @@ -1319,18 +1319,18 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) } for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) { - writel_relaxed(state->trcacvr[i], + writeq_relaxed(state->trcacvr[i], drvdata->base + TRCACVRn(i)); - writel_relaxed(state->trcacatr[i], + writeq_relaxed(state->trcacatr[i], drvdata->base + TRCACATRn(i)); } for (i = 0; i < drvdata->numcidc; i++) - writel_relaxed(state->trccidcvr[i], + writeq_relaxed(state->trccidcvr[i], drvdata->base + TRCCIDCVRn(i)); for (i = 0; i < drvdata->numvmidc; i++) - writel_relaxed(state->trcvmidcvr[i], + writeq_relaxed(state->trcvmidcvr[i], drvdata->base + TRCVMIDCVRn(i)); writel_relaxed(state->trccidcctlr0, drvdata->base + TRCCIDCCTLR0); diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 7da022e87218..b8283e1d6d88 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -334,7 +334,7 @@ struct etmv4_save_state { u64 trcacvr[ETM_MAX_SINGLE_ADDR_CMP]; u64 trcacatr[ETM_MAX_SINGLE_ADDR_CMP]; u64 trccidcvr[ETMv4_MAX_CTXID_CMP]; - u32 trcvmidcvr[ETM_MAX_VMID_CMP]; + u64 trcvmidcvr[ETM_MAX_VMID_CMP]; u32 trccidcctlr0; u32 trccidcctlr1; u32 trcvmidcctlr0;