From patchwork Tue Sep 15 14:12:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Kroah-Hartman X-Patchwork-Id: 263928 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB2A2C31E40 for ; Tue, 15 Sep 2020 23:34:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 803CC21D91 for ; Tue, 15 Sep 2020 23:34:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1600212883; bh=AVqPuBkTTjcguZkuosZqOamQYFdo3B3gnE6D204M4To=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=wMUfSyMdBqSW8kdGiuZZFLZ6buxzNLwy1BfpiYrwLo7miSwdn7IWL7UJ8Tiy9BJqC 5Dfv7K2Q2WTYF6Ri9g0ciITpm6pZufPEyTa1sYoT+uMw4jC3mpqgiZ0FkRVlmg7iJw /EkiF9y6ROjiTaXtP0ZJSAgtDX/6Ssf4utz+J1sk= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727396AbgIOXem (ORCPT ); Tue, 15 Sep 2020 19:34:42 -0400 Received: from mail.kernel.org ([198.145.29.99]:46458 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727148AbgIOOgT (ORCPT ); Tue, 15 Sep 2020 10:36:19 -0400 Received: from localhost (83-86-74-64.cable.dynamic.v4.ziggo.nl [83.86.74.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 0BCCA223BE; Tue, 15 Sep 2020 14:26:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1600179984; bh=AVqPuBkTTjcguZkuosZqOamQYFdo3B3gnE6D204M4To=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=c96cSIHKa/6dXwfGrozZUgmxKFyA0HBUL7+mnpiXsOR399HGTHkOPrEx+UGofsRtC LgsmoqGEkJEAWI9jvxJ//tWRZu0zC1H7rBa8l+yEkV4ds2ksp+yIqnE5eUsO8qKP6o xFRLX0p0yW91QQHKshBEQNJZ2Lgaz+Ti9+huZ46s= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Jiaxun Yang , Huacai Chen , Thomas Bogendoerfer , Sasha Levin Subject: [PATCH 5.8 063/177] MIPS: Loongson64: Do not override watch and ejtag feature Date: Tue, 15 Sep 2020 16:12:14 +0200 Message-Id: <20200915140656.652558424@linuxfoundation.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200915140653.610388773@linuxfoundation.org> References: <20200915140653.610388773@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Jiaxun Yang [ Upstream commit 433c1ca0d441ee0b88fdd83c84ee6d6d43080dcd ] Do not override ejtag feature to 0 as Loongson 3A1000+ do have ejtag. For watch, as KVM emulated CPU doesn't have watch feature, we should not enable it unconditionally. Signed-off-by: Jiaxun Yang Reviewed-by: Huacai Chen Signed-off-by: Thomas Bogendoerfer Signed-off-by: Sasha Levin --- arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h index b6e9c99b85a52..eb181224eb4c4 100644 --- a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h @@ -26,7 +26,6 @@ #define cpu_has_counter 1 #define cpu_has_dc_aliases (PAGE_SIZE < 0x4000) #define cpu_has_divec 0 -#define cpu_has_ejtag 0 #define cpu_has_inclusive_pcaches 1 #define cpu_has_llsc 1 #define cpu_has_mcheck 0 @@ -42,7 +41,6 @@ #define cpu_has_veic 0 #define cpu_has_vint 0 #define cpu_has_vtag_icache 0 -#define cpu_has_watch 1 #define cpu_has_wsbh 1 #define cpu_has_ic_fills_f_dc 1 #define cpu_hwrena_impl_bits 0xc0000000