From patchwork Tue Sep 29 11:00:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Kroah-Hartman X-Patchwork-Id: 291166 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BA89C4741F for ; Tue, 29 Sep 2020 11:17:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 21D0E20848 for ; Tue, 29 Sep 2020 11:17:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1601378255; bh=LiQ50zNWaDoqN8dsTtDdIN6nIuc4ml902OZuUoJUDJA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=O0Hey1htFA0UhOfYzozCNHDhF5UFMq6ejq7PsOs1ExCJN0EdHeoVN5USOOgeNfTWD t8NmiTD2LUb8gDM+BAODrGEt1880HdKPNQpEM8MJh5qeVkr5BBlvlNbrHrig3XKN9H UFaGy+35i+HgHeoSljBi470YtC64UGCbkyMASFCI= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729320AbgI2LRb (ORCPT ); Tue, 29 Sep 2020 07:17:31 -0400 Received: from mail.kernel.org ([198.145.29.99]:34336 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729647AbgI2LR3 (ORCPT ); Tue, 29 Sep 2020 07:17:29 -0400 Received: from localhost (83-86-74-64.cable.dynamic.v4.ziggo.nl [83.86.74.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id B8778206DB; Tue, 29 Sep 2020 11:17:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1601378249; bh=LiQ50zNWaDoqN8dsTtDdIN6nIuc4ml902OZuUoJUDJA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nfZ0ePV4oYo8wb8bXw+kkZierIziDkxYNfWrfnU3vKA+rMzeC6mX5M0YliETTdg1B mUlOyRyw0b8myu5mgnR4yqD+13VKUVZWzqf+N7/WL+eVQ/tYkM0pOB1q1MWMPwHRSw klyCFyGcltBOdec7MrcZdKQkAJtO1Ukj0iPuid5w= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Jonathan Bakker , Kishon Vijay Abraham I , Sasha Levin Subject: [PATCH 4.14 113/166] phy: samsung: s5pv210-usb2: Add delay after reset Date: Tue, 29 Sep 2020 13:00:25 +0200 Message-Id: <20200929105940.844175128@linuxfoundation.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200929105935.184737111@linuxfoundation.org> References: <20200929105935.184737111@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Jonathan Bakker [ Upstream commit 05942b8c36c7eb5d3fc5e375d4b0d0c49562e85d ] The USB phy takes some time to reset, so make sure we give it to it. The delay length was taken from the 4x12 phy driver. This manifested in issues with the DWC2 driver since commit fe369e1826b3 ("usb: dwc2: Make dwc2_readl/writel functions endianness-agnostic.") where the endianness check would read the DWC ID as 0 due to the phy still resetting, resulting in the wrong endian mode being chosen. Signed-off-by: Jonathan Bakker Link: https://lore.kernel.org/r/BN6PR04MB06605D52502816E500683553A3D10@BN6PR04MB0660.namprd04.prod.outlook.com Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sasha Levin --- drivers/phy/samsung/phy-s5pv210-usb2.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/phy/samsung/phy-s5pv210-usb2.c b/drivers/phy/samsung/phy-s5pv210-usb2.c index f6f72339bbc32..bb7fdf491c1c2 100644 --- a/drivers/phy/samsung/phy-s5pv210-usb2.c +++ b/drivers/phy/samsung/phy-s5pv210-usb2.c @@ -142,6 +142,10 @@ static void s5pv210_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on) udelay(10); rst &= ~rstbits; writel(rst, drv->reg_phy + S5PV210_UPHYRST); + /* The following delay is necessary for the reset sequence to be + * completed + */ + udelay(80); } else { pwr = readl(drv->reg_phy + S5PV210_UPHYPWR); pwr |= phypwr;