From patchwork Mon Apr 19 10:28:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Catalin Marinas X-Patchwork-Id: 423982 Delivered-To: patch@linaro.org Received: by 2002:a02:6a6f:0:0:0:0:0 with SMTP id m47csp2583976jaf; Mon, 19 Apr 2021 03:29:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy1WfG8iOJUJFYD8H1oJBIs9t64xzbg8KvUwmiba0uznvKeSEThSsCkZaUbOS2mXVj7ANWp X-Received: by 2002:a17:90a:448b:: with SMTP id t11mr23620083pjg.21.1618828147700; Mon, 19 Apr 2021 03:29:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618828147; cv=none; d=google.com; s=arc-20160816; b=wuVSP4jlCrrgiGee4/e86IpWyovXX4BVokNPWUNFxNT6yR51y6zruiVod7HY9yJmAf NHFhDytlXYtB4u2+IpuvfczPfbJZvqmDlRlX2UzmzN2EnsHYbDbtbTt0FcR4PvJcjTDH oAyr3MzKi0ZLN0EzH4o6mftCR0WpLT71tNqMspPAAeGC1kC4YOeZ4w8Y2J6NYRyz24fm 6WtzK1H3yQnNcyq2mcofm6x6886McUZtXHBdahThMKJ1yYnjEJW+KSdrX3ZB5UdDqaDn CH3umzPOnyNvslGJeUeHFCagp3ZVZAyReNIHwXmwM0+pVfOfnkibxOwCHlDB5QatPV4B cxsw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=BXF3TwokAh10mle0lzfIrpZCII1hcNgFY3A+6dsyqH0=; b=W9we6HSGCFmymkaZa0OQZ5rfLhAStvJckvK+KVp2rA4L9re/E6Hiy2DsOgXL7D/E6k 6hTH1CSiv8ScWU33CCYWQAc/f96CeUTMgagNnhlvD3nZoqRXI80Z4MUR6BcOT20Yp8FY j7Cm2Ah/cFQv2yZYRWBF6oR9hfnuz7j6cgNh25iHg3Hp3Nq+heVSHtgWCRxtF6FiLWXc MaYmmmXzL+b96r6lNluyUFKy7VE9uVMdr/8VYt8Ozre1jgvH0B19/0TLDsSMn+3tZE9L oTNKJd4Gjv8lqYzxNAGIIJKFXKoaxSfY9sx23pIGhb0nHbG3R4jLyPRiZpX2Pagz5xva e1vw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id e12si9189579plt.215.2021.04.19.03.29.07; Mon, 19 Apr 2021 03:29:07 -0700 (PDT) Received-SPF: pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238174AbhDSK3b (ORCPT + 12 others); Mon, 19 Apr 2021 06:29:31 -0400 Received: from mail.kernel.org ([198.145.29.99]:51004 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238651AbhDSK3a (ORCPT ); Mon, 19 Apr 2021 06:29:30 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 2E64A611CE; Mon, 19 Apr 2021 10:29:00 +0000 (UTC) From: Catalin Marinas To: , Greg Kroah-Hartman Cc: Catalin Marinas , Will Deacon , Vincenzo Frascino , Mark Rutland Subject: [PATCH stable 5.10.x] arm64: mte: Ensure TIF_MTE_ASYNC_FAULT is set atomically Date: Mon, 19 Apr 2021 11:28:49 +0100 Message-Id: <20210419102849.2526-1-catalin.marinas@arm.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org commit 2decad92f4731fac9755a083fcfefa66edb7d67d upstream. The entry from EL0 code checks the TFSRE0_EL1 register for any asynchronous tag check faults in user space and sets the TIF_MTE_ASYNC_FAULT flag. This is not done atomically, potentially racing with another CPU calling set_tsk_thread_flag(). Replace the non-atomic ORR+STR with an STSET instruction. While STSET requires ARMv8.1 and an assembler that understands LSE atomics, the MTE feature is part of ARMv8.5 and already requires an updated assembler. Signed-off-by: Catalin Marinas Fixes: 637ec831ea4f ("arm64: mte: Handle synchronous and asynchronous tag check faults") Cc: # 5.10.x Reported-by: Will Deacon Cc: Will Deacon Cc: Vincenzo Frascino Cc: Mark Rutland Link: https://lore.kernel.org/r/20210409173710.18582-1-catalin.marinas@arm.com Signed-off-by: Will Deacon --- arch/arm64/Kconfig | 6 +++++- arch/arm64/kernel/entry.S | 10 ++++++---- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index c1be64228327..5e5cf3af6351 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1390,10 +1390,13 @@ config ARM64_PAN The feature is detected at runtime, and will remain as a 'nop' instruction if the cpu does not implement the feature. +config AS_HAS_LSE_ATOMICS + def_bool $(as-instr,.arch_extension lse) + config ARM64_LSE_ATOMICS bool default ARM64_USE_LSE_ATOMICS - depends on $(as-instr,.arch_extension lse) + depends on AS_HAS_LSE_ATOMICS config ARM64_USE_LSE_ATOMICS bool "Atomic instructions" @@ -1667,6 +1670,7 @@ config ARM64_MTE bool "Memory Tagging Extension support" default y depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI + depends on AS_HAS_LSE_ATOMICS select ARCH_USES_HIGH_VMA_FLAGS help Memory Tagging (part of the ARMv8.5 Extensions) provides diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index d72c818b019c..2da82c139e1c 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -148,16 +148,18 @@ alternative_cb_end .endm /* Check for MTE asynchronous tag check faults */ - .macro check_mte_async_tcf, flgs, tmp + .macro check_mte_async_tcf, tmp, ti_flags #ifdef CONFIG_ARM64_MTE + .arch_extension lse alternative_if_not ARM64_MTE b 1f alternative_else_nop_endif mrs_s \tmp, SYS_TFSRE0_EL1 tbz \tmp, #SYS_TFSR_EL1_TF0_SHIFT, 1f /* Asynchronous TCF occurred for TTBR0 access, set the TI flag */ - orr \flgs, \flgs, #_TIF_MTE_ASYNC_FAULT - str \flgs, [tsk, #TSK_TI_FLAGS] + mov \tmp, #_TIF_MTE_ASYNC_FAULT + add \ti_flags, tsk, #TSK_TI_FLAGS + stset \tmp, [\ti_flags] msr_s SYS_TFSRE0_EL1, xzr 1: #endif @@ -207,7 +209,7 @@ alternative_else_nop_endif disable_step_tsk x19, x20 /* Check for asynchronous tag check faults in user space */ - check_mte_async_tcf x19, x22 + check_mte_async_tcf x22, x23 apply_ssbd 1, x22, x23 ptrauth_keys_install_kernel tsk, x20, x22, x23