From patchwork Fri May 14 10:24:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 438831 Delivered-To: patch@linaro.org Received: by 2002:a02:b78d:0:0:0:0:0 with SMTP id f13csp206426jam; Fri, 14 May 2021 03:25:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxLQhfbqqHMzZw+68EVM3zRRSU9XFX1ikwgZQb/bzGGifwRMImoStmtgRGOO8cclM9Osurh X-Received: by 2002:a05:6e02:148:: with SMTP id j8mr28446132ilr.196.1620987919092; Fri, 14 May 2021 03:25:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620987919; cv=none; d=google.com; s=arc-20160816; b=VFUX6l12eWa2ddeBsOH3Jf1uNHHGHuXupqFfMrPov9MGPzigVM8OPDvo5XA2JHJnaj lCDLMGZ/n4VZWScSyvWZlmuLuQfehNrpn+ynrS1jRKiB4y0T/ef6ubEbL6bz2dUhEJt/ qhenmBhu0Ke6WvT03fAbhCCvVvhvm3UDHfGAnymoq8p57iXFyxHE3i/dIusyL1LqoeUF gmOnKbALY0gWaevp+8q3sbjz5fU/BigZEtfK9ragPZTmHQVOa06Z9OUggDX9yBft+XyJ CcNRIWJchRxUhAe+BzeYk7hhgphpBqCSaKvI8s+ZwVt8vuqlTFqxnmDWMBgFgQGb+fPk gTvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:kerneversion :mime-version:message-id:date:subject:cc:to:from:dkim-signature; bh=YRK450NrvcP5NIJNSckO3Qpug1N4xLcVA9J7LkT5Rlo=; b=LocNWMAzzDcccwB/8lMSbGnr9t4eJq9KHU0rUO9/u+fucQQNYCkychEQJJa+Qt/ocV P5vO5D8hzOtG2Cf7SjBviWEc7DPDU6jM3WJflCd3S0mhwM2p0OR/Ojh6xsuBwuriK268 UpyzXkVba/0UT4PbTwdDYTO3pPKhDM+iuW2WMa3D4lKa0xw7uWri2eIY7FxWaWFX1XaE Wi3CC/KuaQJ55d+TW2TCEcif6MO93oR5iI+6wgFfSkThjb97tzh7XHS3L1kDrOO3P7se h1NCBGh8mLUDzk8/4nmEBcqCxmqKElC14WcRlB0Nmp3sz6tG4HrJeVO0qReK2UDkxzc8 MwIg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=IIbcgTjI; spf=pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id p9si7188606iov.92.2021.05.14.03.25.18; Fri, 14 May 2021 03:25:19 -0700 (PDT) Received-SPF: pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=IIbcgTjI; spf=pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232304AbhENK03 (ORCPT + 12 others); Fri, 14 May 2021 06:26:29 -0400 Received: from mail.kernel.org ([198.145.29.99]:39314 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230295AbhENK02 (ORCPT ); Fri, 14 May 2021 06:26:28 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 2739B61353; Fri, 14 May 2021 10:25:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1620987917; bh=Z7qjumW/icN4UH3B4ep1Ak1pKgALbptrCj4nzrkykbk=; h=From:To:Cc:Subject:Date:From; b=IIbcgTjIXXic0Z/gayWh4cf4wOJwxe8lAxlHwlSuwfqC7fiszgR5g52APrGfjxAQG pfZ19A1V2I1m0z1D80GUx5N7oGLTqbPkm0vAE5h9uzayxbeMIg0MpL160A7jDmRcjC YqUYF6TcD9NVyWDEFxXpgVAzJt7gCmaHnawE/zJKQxHAidUTMnKheFMlxpHrJirqou ++5zN027BvmEHCwsvKGQ37EY+F8OqjoOggkKu4VkDtc0NBIE8y2Of68dZdo0eI1FlB 0zTzx6dvop1RwTVg4kvLw0ynq/xeq8PHHwSckHaJeN2JSxvrYHYVl2kOMBzfrbLYHz oHZxYkk0/rKVQ== From: Arnd Bergmann To: patches@armlinux.org.uk Cc: Arnd Bergmann , stable@vger.kernel.org, Daniel Thompson , Marek Vasut , Ard Biesheuvel Subject: [PATCH] ARM: fix gcc-10 thumb2-kernel regression Date: Fri, 14 May 2021 12:24:10 +0200 Message-Id: <20210514102411.3996120-1-arnd@kernel.org> X-Mailer: git-send-email 2.29.2 MIME-Version: 1.0 KerneVersion: v5.13-rc1 Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Arnd Bergmann When building the kernel wtih gcc-10 or higher using the CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y flag, the compiler picks a slightly different set of registers for the inline assembly in cpu_init() that subsequently results in a corrupt kernel stack as well as remaining in FIQ mode. If a banked register is used for the last argument, the wrong version of that register gets loaded into CPSR_c. When building in Arm mode, the arguments are passed as immediate values and the bug cannot happen. This got introduced when Daniel reworked the FIQ handling and was technically always broken, but happened to work with both clang and gcc before gcc-10 as long as they picked one of the lower registers. This is probably an indication that still very few people build the kernel in Thumb2 mode. Marek pointed out the problem on IRC, Arnd narrowed it down to this inline assembly and Russell pinpointed the exact bug. Change the constraints to force the final mode switch to use a non-banked register for the argument to ensure that the correct constant gets loaded. Another alternative would be to always use registers for the constant arguments to avoid the #ifdef that has now become more complex. Cc: # v3.18+ Cc: Daniel Thompson Reported-by: Marek Vasut Acked-by: Ard Biesheuvel Fixes: c0e7f7ee717e ("ARM: 8150/3: fiq: Replace default FIQ handler") Signed-off-by: Arnd Bergmann --- arch/arm/kernel/setup.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) -- 2.29.2 diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 1a5edf562e85..73ca7797b92f 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -545,9 +545,11 @@ void notrace cpu_init(void) * In Thumb-2, msr with an immediate value is not allowed. */ #ifdef CONFIG_THUMB2_KERNEL -#define PLC "r" +#define PLC_l "l" +#define PLC_r "r" #else -#define PLC "I" +#define PLC_l "I" +#define PLC_r "I" #endif /* @@ -569,15 +571,15 @@ void notrace cpu_init(void) "msr cpsr_c, %9" : : "r" (stk), - PLC (PSR_F_BIT | PSR_I_BIT | IRQ_MODE), + PLC_r (PSR_F_BIT | PSR_I_BIT | IRQ_MODE), "I" (offsetof(struct stack, irq[0])), - PLC (PSR_F_BIT | PSR_I_BIT | ABT_MODE), + PLC_r (PSR_F_BIT | PSR_I_BIT | ABT_MODE), "I" (offsetof(struct stack, abt[0])), - PLC (PSR_F_BIT | PSR_I_BIT | UND_MODE), + PLC_r (PSR_F_BIT | PSR_I_BIT | UND_MODE), "I" (offsetof(struct stack, und[0])), - PLC (PSR_F_BIT | PSR_I_BIT | FIQ_MODE), + PLC_r (PSR_F_BIT | PSR_I_BIT | FIQ_MODE), "I" (offsetof(struct stack, fiq[0])), - PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE) + PLC_l (PSR_F_BIT | PSR_I_BIT | SVC_MODE) : "r14"); #endif }