From patchwork Mon May 17 14:01:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Kroah-Hartman X-Patchwork-Id: 440111 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp1139431jac; Mon, 17 May 2021 07:25:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwQJ3SKjtesGifSdsZo2bJOI9twTjHoPOk4gauP2VYHCD0cDURvNlYcUJsLRw0Sc0mG7UkC X-Received: by 2002:aa7:c782:: with SMTP id n2mr334913eds.77.1621261540846; Mon, 17 May 2021 07:25:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1621261540; cv=none; d=google.com; s=arc-20160816; b=ttSYE8BqSRUo+3XcqYZoQ34tNSs/z62veqFLEYSPzm99j3ld6R1j6bey3cOt9gEsRP YDOLCAEVrOLVeEw0btrQsFkvKE+AP6B6/g5oOHuOQfaNW4u24pNk/ewPyDJSAt2a1pmZ v2PVLkExceWj1n5jlFF8+jY9lXCukbXRQ/CZ3A5zVfmKUmQPG0yLvLZspVAcRkUOVhp7 XP5hzcZtvEaJxXGx1NUjYjsTabpfa2Lee0YZmr0q92YZNzYNmzhik6NJCAyDZBwaLyiz mZsCyiWI06J1loHaflcGVnOb3zfgT5RqyMmXXtEnvMNHVba0C4O+9ptM1epJZKhHPAs1 c8kA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :user-agent:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=GY7BhKJ7SuKiZK98c+xMflSIuNwOzQKfxmZTeMnZong=; b=qzoGVbAPz9IzQkTEtxkZJkZvjuXeQY2SlZ3aKpl544ch/vcp9GlHZRAMUPUzcgs4Ox bxq7qH35H/JXpoc+cXKnQeX086DXjqn+GlEZ4MkClp+H5Qs0yDpQpbOLKP7Jsdd8xBzj uEMRR8e90zVKCldBZDDUvWpEiiQCokBJVRkBwomn7J4bZ9Yjt6pYim3l1Y5s2jDwhyoR Jd2bbsROtu2/A7vZuJ144F/YPEv5GxUDlNJr/YbpDZnCXb52kj3MIIV+mqhoZ4CNJGBe SxmajHHhk4fIf8u+izhtJ6+/KrskqgD4zJzY0/gJaEME9hMj/npyG7MyYiAgb13pNN6r popQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linuxfoundation.org header.s=korg header.b=AXtIAzSl; spf=pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linuxfoundation.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id m18si1890092edd.534.2021.05.17.07.25.40; Mon, 17 May 2021 07:25:40 -0700 (PDT) Received-SPF: pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linuxfoundation.org header.s=korg header.b=AXtIAzSl; spf=pass (google.com: domain of stable-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linuxfoundation.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236148AbhEQO0v (ORCPT + 12 others); Mon, 17 May 2021 10:26:51 -0400 Received: from mail.kernel.org ([198.145.29.99]:54920 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239731AbhEQOYp (ORCPT ); Mon, 17 May 2021 10:24:45 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 94B5161468; Mon, 17 May 2021 14:13:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1621260787; bh=IW3qTF8Pc10N5Jh1/q7Dj1ZdQhjrIiziEjyYlFZMsEo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AXtIAzSlfLgSLJ3utuELZIoV1wIE7jYnNnuTmknfyYEHE9zLZzWM4rig4aYrVPKgh W6hIxJqvAgTDqjS3lv7X+58+Jm7m6JUs9V1yb/7GJtipqm2wHl50kKyT2mUrLtgkeF J6mpF3AlWGZCRNkPQy3l+1Qzn8KwoFYIxptjgwSo= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Alex Elder , Jakub Kicinski , Sasha Levin Subject: [PATCH 5.12 236/363] net: ipa: fix inter-EE IRQ register definitions Date: Mon, 17 May 2021 16:01:42 +0200 Message-Id: <20210517140310.564727583@linuxfoundation.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210517140302.508966430@linuxfoundation.org> References: <20210517140302.508966430@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Alex Elder [ Upstream commit 6a780f51f87b430cc69ebf4e859e7e9be720b283 ] In gsi_irq_setup(), two registers are written with the intention of disabling inter-EE channel and event IRQs. But the wrong registers are used (and defined); the ones used are read-only registers that indicate whether the interrupt condition is present. Define the mask registers instead of the status registers, and use them to disable the inter-EE interrupt types. Fixes: 46f748ccaf01 ("net: ipa: explicitly disallow inter-EE interrupts") Signed-off-by: Alex Elder Link: https://lore.kernel.org/r/20210505223636.232527-1-elder@linaro.org Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/ipa/gsi.c | 4 ++-- drivers/net/ipa/gsi_reg.h | 18 +++++++++--------- 2 files changed, 11 insertions(+), 11 deletions(-) -- 2.30.2 diff --git a/drivers/net/ipa/gsi.c b/drivers/net/ipa/gsi.c index 390d3403386a..144892060718 100644 --- a/drivers/net/ipa/gsi.c +++ b/drivers/net/ipa/gsi.c @@ -211,8 +211,8 @@ static void gsi_irq_setup(struct gsi *gsi) iowrite32(0, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET); /* The inter-EE registers are in the non-adjusted address range */ - iowrite32(0, gsi->virt_raw + GSI_INTER_EE_SRC_CH_IRQ_OFFSET); - iowrite32(0, gsi->virt_raw + GSI_INTER_EE_SRC_EV_CH_IRQ_OFFSET); + iowrite32(0, gsi->virt_raw + GSI_INTER_EE_SRC_CH_IRQ_MSK_OFFSET); + iowrite32(0, gsi->virt_raw + GSI_INTER_EE_SRC_EV_CH_IRQ_MSK_OFFSET); iowrite32(0, gsi->virt + GSI_CNTXT_GSI_IRQ_EN_OFFSET); } diff --git a/drivers/net/ipa/gsi_reg.h b/drivers/net/ipa/gsi_reg.h index 1622d8cf8dea..48ef04afab79 100644 --- a/drivers/net/ipa/gsi_reg.h +++ b/drivers/net/ipa/gsi_reg.h @@ -53,15 +53,15 @@ #define GSI_EE_REG_ADJUST 0x0000d000 /* IPA v4.5+ */ /* The two inter-EE IRQ register offsets are relative to gsi->virt_raw */ -#define GSI_INTER_EE_SRC_CH_IRQ_OFFSET \ - GSI_INTER_EE_N_SRC_CH_IRQ_OFFSET(GSI_EE_AP) -#define GSI_INTER_EE_N_SRC_CH_IRQ_OFFSET(ee) \ - (0x0000c018 + 0x1000 * (ee)) - -#define GSI_INTER_EE_SRC_EV_CH_IRQ_OFFSET \ - GSI_INTER_EE_N_SRC_EV_CH_IRQ_OFFSET(GSI_EE_AP) -#define GSI_INTER_EE_N_SRC_EV_CH_IRQ_OFFSET(ee) \ - (0x0000c01c + 0x1000 * (ee)) +#define GSI_INTER_EE_SRC_CH_IRQ_MSK_OFFSET \ + GSI_INTER_EE_N_SRC_CH_IRQ_MSK_OFFSET(GSI_EE_AP) +#define GSI_INTER_EE_N_SRC_CH_IRQ_MSK_OFFSET(ee) \ + (0x0000c020 + 0x1000 * (ee)) + +#define GSI_INTER_EE_SRC_EV_CH_IRQ_MSK_OFFSET \ + GSI_INTER_EE_N_SRC_EV_CH_IRQ_MSK_OFFSET(GSI_EE_AP) +#define GSI_INTER_EE_N_SRC_EV_CH_IRQ_MSK_OFFSET(ee) \ + (0x0000c024 + 0x1000 * (ee)) /* All other register offsets are relative to gsi->virt */ #define GSI_CH_C_CNTXT_0_OFFSET(ch) \