List-Id: U-Boot discussion <u-boot.lists.denx.de> From: chee.hong.ang at intel.com (Chee Hong Ang) Date: Fri, 10 Jul 2020 20:55:19 +0800 Subject: [PATCH v1 0/4] Agilex's clock driver updates and fixes Message-ID: <20200710125523.68008-1-chee.hong.ang@intel.com>
- Add clock enable. - Add clock source for NAND. - Add additional PLL configurations via mebus writes. - U-Boot proper will not re-initialize the clock again if it's already initialized by SPL. Chee Hong Ang (2): clk: agilex: Handle clock configuration differently in SPL and U-Boot proper clk: agilex: Additional membus writes for HPS PLL Ley Foon Tan (2): clk: agilex: Add NAND clock support clk: agilex: Add clock enable support drivers/clk/altera/clk-agilex.c | 113 +++++++++++++++++++++++++++----- 1 file changed, 97 insertions(+), 16 deletions(-)
- Add clock enable. - Add clock source for NAND. - Add additional PLL configurations via mebus writes. - U-Boot proper will not re-initialize the clock again if it's already initialized by SPL. Chee Hong Ang (2): clk: agilex: Handle clock configuration differently in SPL and U-Boot proper clk: agilex: Additional membus writes for HPS PLL Ley Foon Tan (2): clk: agilex: Add NAND clock support clk: agilex: Add clock enable support drivers/clk/altera/clk-agilex.c | 113 +++++++++++++++++++++++++++----- 1 file changed, 97 insertions(+), 16 deletions(-)