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[92.17.96.232]) by smtp.gmail.com with ESMTPSA id p7-20020a05600c358700b004182cd07133sm9040333wmq.3.2024.04.15.08.03.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Apr 2024 08:03:40 -0700 (PDT) From: Caleb Connolly Subject: [PATCH v2 0/3] qcom: serial_msm: calculate UARTDM_CSR automatically Date: Mon, 15 Apr 2024 16:03:37 +0100 Message-Id: <20240415-b4-msm-serial-bitrate-v2-0-b7a048adc6a3@linaro.org> MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAMlBHWYC/4WNQQqDMBBFryKz7pQkJFW76j2Ki6SOOqCmTERax Ls3eoEu34f3/gaJhCnBvdhAaOXEcc5gLgW8Bj/3hNxmBqOMVVY7DBanNOGh+REDL+IXwvIWXO2 0Mq6sILtvoY4/Z/fZZB44LVG+582qj/VfcdWo0Pmq7irbtTWVj5FnL/EapYdm3/cfeLJou7sAA AA= To: Lukasz Majewski , Sean Anderson , Caleb Connolly , Neil Armstrong , Sumit Garg , Tom Rini Cc: Robert Marko , u-boot-qcom@groups.io, u-boot@lists.denx.de X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=1273; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=eJLnmgtbB0r98smCsMhvCu5LhrP3X4FmPY57YOffVp4=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhjRZx9MG7lbaDVMrLLflq0dcmizJoyI323L34vapxc5mL 8yN4zI7SlkYBDkYZMUUWcRPLLNsWnvZXmP7ggswc1iZQIYwcHEKwESsohn+F0iuKNldl/3t8CL/ WZNPmLy9PPH3M9OLkveVqkoX75isoMfwP3ZHiZrTW+sHxnzqmpK3ps8xtnypfJDf2Z5//spqhd2 HuQA= X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The msm serial UART controller has a bit clock divider register which much be programmed based on the UART clock. This changes per soc and currently is expected to be specified in DT or otherwise selected per board. This series fixes the apq8016 and ipq4019 clock drivers to return the programmed UART clock rate in clk_set_rate(), it then uses this clock rate and the hardcoded baud rate supported by this driver to calculate the correct value for the UARTDM_CSR register. --- Changes in v2: - use CONFIG_VAL(DEBUG_UART_CLOCK) for debug uart clk_rate. - Link to v1: https://lore.kernel.org/r/20240415-b4-msm-serial-bitrate-v1-0-5a89f84fd9e7@linaro.org --- Caleb Connolly (3): clk/qcom: apq8016: return valid rate when setting UART clock clk/qcom: ipq4019: return valid rate when setting UART clock serial: msm: calculate bit clock divider doc/device-tree-bindings/serial/msm-serial.txt | 10 --- drivers/clk/qcom/clock-apq8016.c | 4 +- drivers/clk/qcom/clock-ipq4019.c | 2 +- drivers/serial/serial_msm.c | 87 +++++++++++++++++++++----- 4 files changed, 73 insertions(+), 30 deletions(-) --- base-commit: 42f6978987336cff3d98d9cc4643c54a1eb0f36d // Caleb (they/them)