From patchwork Wed Apr 13 13:25:40 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Hui X-Patchwork-Id: 997 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:48:08 -0000 Delivered-To: patches@linaro.org Received: by 10.68.59.138 with SMTP id z10cs309566pbq; Wed, 13 Apr 2011 06:27:04 -0700 (PDT) Received: by 10.150.134.13 with SMTP id h13mr498351ybd.219.1302701223399; Wed, 13 Apr 2011 06:27:03 -0700 (PDT) Received: from mail-yi0-f50.google.com (mail-yi0-f50.google.com [209.85.218.50]) by mx.google.com with ESMTPS id w18si1601590ybe.10.2011.04.13.06.27.01 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 13 Apr 2011 06:27:02 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.218.50 is neither permitted nor denied by best guess record for domain of jason.hui@linaro.org) client-ip=209.85.218.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.218.50 is neither permitted nor denied by best guess record for domain of jason.hui@linaro.org) smtp.mail=jason.hui@linaro.org Received: by yie30 with SMTP id 30so476665yie.37 for ; Wed, 13 Apr 2011 06:27:01 -0700 (PDT) Received: by 10.43.57.211 with SMTP id wh19mr3201239icb.1.1302701221598; Wed, 13 Apr 2011 06:27:01 -0700 (PDT) Received: from localhost.localdomain ([116.231.118.83]) by mx.google.com with ESMTPS id i20sm443347iby.31.2011.04.13.06.26.18 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 13 Apr 2011 06:27:00 -0700 (PDT) From: Jason Liu To: u-boot@lists.denx.de Cc: sbabic@denx.de Subject: [U-Boot][PATCH V1 1/1] MX5: Keep L2 cache enabled before jump to kernel Date: Wed, 13 Apr 2011 21:25:40 +0800 Message-Id: <1302701143-10624-1-git-send-email-jason.hui@linaro.org> X-Mailer: git-send-email 1.7.0.4 Currently, Linux kernel does not do any L2 cache enable Operation.So,Keep L2 cache enabled(L2EN=1) in the u-boot before Jump to the Linux Kernel and thus L2 cache can be effectively used in Linux Kernel. Signed-off-by: Jason Liu --- arch/arm/cpu/armv7/mx5/Makefile | 2 +- arch/arm/cpu/armv7/mx5/cache.S | 43 +++++++++++++++++++++++++++++ arch/arm/cpu/armv7/mx5/soc.c | 6 ++++ arch/arm/include/asm/arch-mx5/sys_proto.h | 2 + include/configs/mx51evk.h | 2 - include/configs/mx53evk.h | 2 - include/configs/mx53loco.h | 2 - 7 files changed, 52 insertions(+), 7 deletions(-) diff --git a/arch/arm/cpu/armv7/mx5/Makefile b/arch/arm/cpu/armv7/mx5/Makefile index e8be9c9..a7df7a6 100644 --- a/arch/arm/cpu/armv7/mx5/Makefile +++ b/arch/arm/cpu/armv7/mx5/Makefile @@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o COBJS = soc.o clock.o iomux.o timer.o speed.o -SOBJS = lowlevel_init.o +SOBJS = lowlevel_init.o cache.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/arch/arm/cpu/armv7/mx5/cache.S b/arch/arm/cpu/armv7/mx5/cache.S new file mode 100644 index 0000000..c81c8be --- /dev/null +++ b/arch/arm/cpu/armv7/mx5/cache.S @@ -0,0 +1,43 @@ +/* + * Copyright 2011 Linaro Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +.align 5 +.global invalidate_dcache +.global l2_cache_enable +.global l2_cache_disable + +/* + * Sine we did not enable D-cache in uboot,this is the + * Dummy function for L2 ON to make build pass. please + * Check the arch/arm/cpu/armv7/cpu.c file + */ +invalidate_dcache: + mov pc, lr + +l2_cache_enable: + mrc p15, 0, r0, c1, c0, 1; + orr r0, r0, #0x2 + mcr p15, 0, r0, c1, c0, 1; + mov pc, lr + +l2_cache_disable: + mrc p15, 0, r0, c1, c0, 1; + bic r0, r0, #0x2 + mcr p15, 0, r0, c1, c0, 1; + mov pc, lr diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c index 09500b3..e3b6269 100644 --- a/arch/arm/cpu/armv7/mx5/soc.c +++ b/arch/arm/cpu/armv7/mx5/soc.c @@ -144,3 +144,9 @@ void reset_cpu(ulong addr) { __raw_writew(4, WDOG1_BASE_ADDR); } + +/*dummy function for L2 ON*/ +u32 get_device_type(void) +{ + return 0; +} diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h index f687503..89ab8e8 100644 --- a/arch/arm/include/asm/arch-mx5/sys_proto.h +++ b/arch/arm/include/asm/arch-mx5/sys_proto.h @@ -27,5 +27,7 @@ u32 get_cpu_rev(void); #define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) void sdelay(unsigned long); +void invalidate_dcache(u32); +u32 get_device_type(void); #endif diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 50caacd..abf6cb9 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -35,8 +35,6 @@ #define CONFIG_SYS_TEXT_BASE 0x97800000 -#define CONFIG_L2_OFF - #include /* * Disabled for now due to build problems under Debian and a significant diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h index 6ac910b..410795f 100644 --- a/include/configs/mx53evk.h +++ b/include/configs/mx53evk.h @@ -29,8 +29,6 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_L2_OFF - #include #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 9c7dcc9..1e60335 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -30,8 +30,6 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_L2_OFF - #include #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */