From patchwork Thu Apr 14 10:21:24 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chander Kashyap X-Patchwork-Id: 1014 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:48:19 -0000 Delivered-To: patches@linaro.org Received: by 10.68.59.138 with SMTP id z10cs29888pbq; Thu, 14 Apr 2011 03:23:02 -0700 (PDT) Received: by 10.216.81.69 with SMTP id l47mr6157371wee.78.1302776581273; Thu, 14 Apr 2011 03:23:01 -0700 (PDT) Received: from mail-wy0-f178.google.com (mail-wy0-f178.google.com [74.125.82.178]) by mx.google.com with ESMTPS id q11si2694181weh.45.2011.04.14.03.23.00 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 14 Apr 2011 03:23:01 -0700 (PDT) Received-SPF: neutral (google.com: 74.125.82.178 is neither permitted nor denied by best guess record for domain of chander.kashyap@linaro.org) client-ip=74.125.82.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 74.125.82.178 is neither permitted nor denied by best guess record for domain of chander.kashyap@linaro.org) smtp.mail=chander.kashyap@linaro.org Received: by mail-wy0-f178.google.com with SMTP id 33so1518623wyb.37 for ; Thu, 14 Apr 2011 03:23:00 -0700 (PDT) Received: by 10.227.91.81 with SMTP id l17mr644204wbm.29.1302776580305; Thu, 14 Apr 2011 03:23:00 -0700 (PDT) Received: from chander-ubuntu ([115.113.119.130]) by mx.google.com with ESMTPS id p5sm893901wbg.11.2011.04.14.03.22.53 (version=SSLv3 cipher=OTHER); Thu, 14 Apr 2011 03:22:59 -0700 (PDT) From: Chander Kashyap To: u-boot@lists.denx.de Cc: mk7.kang@samsung.com, bjlee@samsung.com, patches@linaro.org, samsung@lists.linaro.org, linaro-dev@lists.linaro.org, Chander Kashyap Subject: [PATCH 1/2] S5P: SROM config code moved to common directory s5p-common Date: Thu, 14 Apr 2011 15:51:24 +0530 Message-Id: <1302776485-28670-2-git-send-email-chander.kashyap@linaro.org> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1302776485-28670-1-git-send-email-chander.kashyap@linaro.org> References: <1302776485-28670-1-git-send-email-chander.kashyap@linaro.org> SROM configuration is same for various S5P series Boards. Signed-off-by: Chander Kashyap --- arch/arm/cpu/armv7/s5p-common/Makefile | 3 +- arch/arm/cpu/armv7/s5p-common/sromc.c | 49 ++++++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+), 1 deletions(-) create mode 100644 arch/arm/cpu/armv7/s5p-common/sromc.c -- 1.7.1 diff --git a/arch/arm/cpu/armv7/s5p-common/Makefile b/arch/arm/cpu/armv7/s5p-common/Makefile index ce0a41e..1705399 100644 --- a/arch/arm/cpu/armv7/s5p-common/Makefile +++ b/arch/arm/cpu/armv7/s5p-common/Makefile @@ -27,7 +27,8 @@ LIB = $(obj)libs5p-common.o COBJS-y += cpu_info.o COBJS-y += timer.o -COBJS-$(CONFIG_PWM) += pwm.o +COBJS-y += sromc.o +COBJS-$(CONFIG_PWM) += pwm.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS)) diff --git a/arch/arm/cpu/armv7/s5p-common/sromc.c b/arch/arm/cpu/armv7/s5p-common/sromc.c new file mode 100644 index 0000000..091e8d1 --- /dev/null +++ b/arch/arm/cpu/armv7/s5p-common/sromc.c @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2010 Samsung Electronics + * Naveen Krishna Ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * s5p_config_sromc() - select the proper SROMC Bank and configure the + * band width control and bank control registers + * srom_bank - SROM + * srom_bw_conf - SMC Band witdh reg configuration value + * srom_bc_conf - SMC Bank Control reg configuration value + */ +void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf) +{ + u32 tmp; + struct s5p_sromc *srom = + (struct s5p_sromc *)samsung_get_base_sromc(); + + /* Configure SMC_BW register to handle proper SROMC bank */ + tmp = srom->bw; + tmp &= ~(0xF << (srom_bank * 4)); + tmp |= srom_bw_conf; + srom->bw = tmp; + + /* Configure SMC_BC register */ + srom->bc[srom_bank] = srom_bc_conf; +}