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[203.254.224.24]) by mx.google.com with ESMTP id oy7si5539110pbc.285.2012.05.25.04.51.15; Fri, 25 May 2012 04:51:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.24 as permitted sender) client-ip=203.254.224.24; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.24 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm1.samsung.com (mailout1.samsung.com [203.254.224.24]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M4K00MD4U9EYMG0@mailout1.samsung.com>; Fri, 25 May 2012 20:51:15 +0900 (KST) X-AuditID: cbfee61a-b7fe76d0000023f5-c0-4fbf7233ad8a Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 24.9C.09205.3327FBF4; Fri, 25 May 2012 20:51:15 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M4K00LCRU6DUZ50@mmp1.samsung.com>; Fri, 25 May 2012 20:51:15 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, afleming@gmail.com, tlambert@chromium.org Subject: [PATCH 1/4] EXYNOS: MSHCI: Add clock for EXYNOS5 Date: Fri, 25 May 2012 17:23:15 +0530 Message-id: <1337946798-1660-2-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1337946798-1660-1-git-send-email-rajeshwari.s@samsung.com> References: <1337946798-1660-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrBJMWRmVeSWpSXmKPExsVy+t9jAV3jov3+BgcOcFk8XH+TxWLK4S8s Dkwed67tYQtgjOKySUnNySxLLdK3S+DK2N7WwVxwSb7ixb0lrA2M3yW7GDk5JARMJPb27GaG sMUkLtxbzwZiCwksYpRoWiDYxcgFZE9kktg29wBYEZuAkcTWk9MYQWwRAQmJX/1XGUGKmAXa GSW6tl0CKxIWsJQ4s+wXO4jNIqAq8XvlHBYQm1fAXWLCgcOsENsUJI5N/Qpmcwp4SNxcsowJ YrO7xJa/q1gnMPIuYGRYxSiaWpBcUJyUnmuoV5yYW1yal66XnJ+7iRHs/2dSOxhXNlgcYhTg YFTi4b0Qs99fiDWxrLgy9xCjBAezkggvSxpQiDclsbIqtSg/vqg0J7X4EKM0B4uSOK/d4h3+ QgLpiSWp2ampBalFMFkmDk6pBsZ1wV06E8RORzNERbJ9vOZ0zc85KLCrLztTsjFsN4Phh5oM uekHqleF8//8eYjdLPG7/OFpkTG/BCXTvm+P3rZy2ctDCgsKRQ9/vqgvv/LT4/RvH7g67ilI /Ynn0/XytPseEtPZEvdvb8R+nfAnYvU9wUFpmt2fUox8pCxls+NnnVTjai+aqMRSnJFoqMVc VJwIAEJ91t77AQAA X-TM-AS-MML: No X-Gm-Message-State: ALoCoQmhW+5Ihrwtl8RYNoqpNlFEXsq3rL9JZgQCQIUg2AjL2+rbONr/jXAhV1qq15KGy4JV2YVI Add apis to set and get divider clock ratio for FSYS_BLK on EXYNOS5. Signed-off-by: Terry Lambert Signed-off-by: Alim Akhtar Signed-off-by: Rajeshwari Shinde Acked-by: Simon Glass --- arch/arm/cpu/armv7/exynos/clock.c | 96 ++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/clk.h | 4 + 2 files changed, 100 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 3b86b0c..3af1aac 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -414,6 +414,90 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div) writel(val, addr); } +static unsigned long exynos5_get_mshci_clk_div(enum periph_id peripheral) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + u32 *addr; + unsigned int div_mmc, div_mmc_pre; + unsigned int mpll_clock, sclk_mmc; + + mpll_clock = get_pll_clk(MPLL); + + /* + * CLK_DIV_FSYS1 + * MMC0_PRE_RATIO [15:8], MMC0_RATIO [3:0] + * CLK_DIV_FSYS2 + * MMC2_PRE_RATIO [15:8], MMC2_RATIO [3:0] + * CLK_DIV_FSYS3 + * MMC4_PRE_RATIO [15:8], MMC4_RATIO [3:0] + */ + switch (peripheral) { + case PERIPH_ID_SDMMC0: + addr = &clk->div_fsys1; + break; + case PERIPH_ID_SDMMC2: + addr = &clk->div_fsys2; + break; + case PERIPH_ID_SDMMC4: + addr = &clk->div_fsys3; + break; + default: + debug("invalid peripheral\n"); + return -1; + } + + div_mmc = (readl(addr) & 0xf) + 1; + div_mmc_pre = ((readl(addr) & 0xff00) >> 8) + 1; + sclk_mmc = (mpll_clock / div_mmc) / div_mmc_pre; + + return sclk_mmc; +} + +static int exynos5_set_mshci_clk_div(enum periph_id peripheral) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + u32 *addr; + unsigned int clock; + unsigned int tmp; + unsigned int i; + + /* get mpll clock */ + clock = get_pll_clk(MPLL) / 1000000; + + /* + * CLK_DIV_FSYS1 + * MMC0_PRE_RATIO [15:8], MMC0_RATIO [3:0] + * CLK_DIV_FSYS2 + * MMC2_PRE_RATIO [15:8], MMC2_RATIO [3:0] + * CLK_DIV_FSYS3 + * MMC4_PRE_RATIO [15:8], MMC4_RATIO [3:0] + */ + switch (peripheral) { + case PERIPH_ID_SDMMC0: + addr = &clk->div_fsys1; + break; + case PERIPH_ID_SDMMC2: + addr = &clk->div_fsys2; + break; + case PERIPH_ID_SDMMC4: + addr = &clk->div_fsys3; + break; + default: + debug("invalid peripheral\n"); + return -1; + } + tmp = readl(addr) & ~0xff0f; + for (i = 0; i <= 0xf; i++) { + if ((clock / (i + 1)) <= 400) { + writel(tmp | i << 0, addr); + break; + } + } + return 0; +} + /* get_lcd_clk: return lcd clock frequency */ static unsigned long exynos4_get_lcd_clk(void) { @@ -651,6 +735,18 @@ void set_mmc_clk(int dev_index, unsigned int div) exynos4_set_mmc_clk(dev_index, div); } +unsigned long get_mshci_clk_div(enum periph_id peripheral) +{ + if (cpu_is_exynos5()) + return exynos5_get_mshci_clk_div(peripheral); +} + +int set_mshci_clk_div(enum periph_id peripheral) +{ + if (cpu_is_exynos5()) + return exynos5_set_mshci_clk_div(peripheral); +} + unsigned long get_lcd_clk(void) { if (cpu_is_exynos4()) diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index 72dc655..4a6fa90 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -22,6 +22,8 @@ #ifndef __ASM_ARM_ARCH_CLK_H_ #define __ASM_ARM_ARCH_CLK_H_ +#include + #define APLL 0 #define MPLL 1 #define EPLL 2 @@ -34,6 +36,8 @@ unsigned long get_i2c_clk(void); unsigned long get_pwm_clk(void); unsigned long get_uart_clk(int dev_index); void set_mmc_clk(int dev_index, unsigned int div); +unsigned long get_mshci_clk_div(enum periph_id peripheral); +int set_mshci_clk_div(enum periph_id peripheral); unsigned long get_lcd_clk(void); void set_lcd_clk(void); void set_mipi_clk(void);