From patchwork Mon Jun 18 16:25:36 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 9399 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 179C723EB4 for ; Mon, 18 Jun 2012 16:26:06 +0000 (UTC) Received: from mail-gh0-f180.google.com (mail-gh0-f180.google.com [209.85.160.180]) by fiordland.canonical.com (Postfix) with ESMTP id DB802A184C1 for ; Mon, 18 Jun 2012 16:26:05 +0000 (UTC) Received: by mail-gh0-f180.google.com with SMTP id z12so4139571ghb.11 for ; Mon, 18 Jun 2012 09:26:05 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=5uybgzWA7nXI9JrclgzCkNVd6N9rM8Jq5RLTA/KJk3A=; b=hXEv6Emy4N+HKcxDpOn2jxr0xKZz4p4C+SJzBTZ6kE5fidX05f44JxLKW+QOYfWupX qRlxckxCyHW7z2IWZyb4h7vLuVUeWF9QntWhkq5LbciLqu+E7c8FjYp/dH9uBdpg8U+M R04q8MN390Vjimc/7doXq1yHX5Etx57IBH4o17BBjZ1DWw+UvJTeGlCycVIc9eeasnBf ivVquq7RQErUwLIzMWY1rc/BjsxNpdHfHNtRVVk+1RCznAtEUgl2rSe1z36ZiHnwsUwf yT9T/qrYzHCF/2QmZ/ktiP8C9EojnxbUs15bMD0COtFJK4MRNc0CtPboZ30+RtQKhkwl mT/A== Received: by 10.50.193.196 with SMTP id hq4mr8983808igc.57.1340036765476; Mon, 18 Jun 2012 09:26:05 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.24.148 with SMTP id v20csp77305ibb; Mon, 18 Jun 2012 09:26:05 -0700 (PDT) Received: by 10.68.204.129 with SMTP id ky1mr55302736pbc.32.1340036764808; Mon, 18 Jun 2012 09:26:04 -0700 (PDT) Received: from mail-pz0-f50.google.com (mail-pz0-f50.google.com [209.85.210.50]) by mx.google.com with ESMTPS id gk9si25764445pbc.338.2012.06.18.09.26.04 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 18 Jun 2012 09:26:04 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.210.50 is neither permitted nor denied by best guess record for domain of mathieu.poirier@linaro.org) client-ip=209.85.210.50; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.210.50 is neither permitted nor denied by best guess record for domain of mathieu.poirier@linaro.org) smtp.mail=mathieu.poirier@linaro.org Received: by mail-pz0-f50.google.com with SMTP id h15so8066502dan.37 for ; Mon, 18 Jun 2012 09:26:04 -0700 (PDT) Received: by 10.68.241.8 with SMTP id we8mr53258292pbc.130.1340036764457; Mon, 18 Jun 2012 09:26:04 -0700 (PDT) Received: from localhost.localdomain (S0106002369de4dac.cg.shawcable.net. [70.73.24.112]) by mx.google.com with ESMTPS id mq8sm51844pbb.64.2012.06.18.09.26.03 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 18 Jun 2012 09:26:03 -0700 (PDT) From: mathieu.poirier@linaro.org To: u-boot@lists.denx.de Cc: patches@linaro.org, mathieu.poirier@linaro.org, lee.jones@linaro.org Subject: [PATCH 11/11] snowball: Adding board specific cache cleanup routine Date: Mon, 18 Jun 2012 10:25:36 -0600 Message-Id: <1340036736-2436-12-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1340036736-2436-1-git-send-email-mathieu.poirier@linaro.org> References: <1340036736-2436-1-git-send-email-mathieu.poirier@linaro.org> X-Gm-Message-State: ALoCoQnzYbm+P4d5SUlMYLG0VAsFxIsaIIu8zDepiSP9Db8L9JI5bqf28Gf22Yms92pLOSkmzqN3 From: "Mathieu J. Poirier" This is mandatory in order to boot the Linux kernel. Signed-off-by: Mathieu Poirier Signed-off-by: John Rigby --- arch/arm/cpu/armv7/u8500/cpu.c | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/u8500/cpu.c b/arch/arm/cpu/armv7/u8500/cpu.c index 02bb332..66a9d2c 100644 --- a/arch/arm/cpu/armv7/u8500/cpu.c +++ b/arch/arm/cpu/armv7/u8500/cpu.c @@ -73,6 +73,15 @@ static unsigned int read_asicid(void) return readl(address); } +void cpu_cache_management(void) +{ + if (cpu_is_u8500v2()) { + *((volatile unsigned int *)(0xA04127CC)) = 0xFF; + *((volatile unsigned int *)(0xA0412900)) = 0xFF; + *((volatile unsigned int *)(0xA0412904)) = 0xFF; + } +} + #ifdef CONFIG_ARCH_CPU_INIT /* * SOC specific cpu init