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[203.254.224.33]) by mx.google.com with ESMTP id gk9si34082495pbc.8.2012.06.20.04.09.30; Wed, 20 Jun 2012 04:09:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.33 as permitted sender) client-ip=203.254.224.33; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.33 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm2.samsung.com (mailout3.samsung.com [203.254.224.33]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M5W00500XNM0290@mailout3.samsung.com>; Wed, 20 Jun 2012 20:09:29 +0900 (KST) X-AuditID: cbfee61b-b7fcc6d000003a7a-98-4fe1af699240 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 7C.F7.14970.96FA1EF4; Wed, 20 Jun 2012 20:09:29 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M5W00K59XJU4P50@mmp1.samsung.com>; Wed, 20 Jun 2012 20:09:29 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, alim.akhtar@samsung.com, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, dofmind@gmail.com Subject: [PATCH 8/9 V2] EXYNOS5 : Modify pinnumx settings as per Exynos5250 Rev 1.0 Date: Wed, 20 Jun 2012 16:41:54 +0530 Message-id: <1340190715-23648-3-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1340190715-23648-1-git-send-email-rajeshwari.s@samsung.com> References: <1340190715-23648-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrBJMWRmVeSWpSXmKPExsVy+t9jAd3M9Q/9DSacMrR4uP4mi8WUw19Y HJg87lzbwxbAGMVlk5Kak1mWWqRvl8CVced0M3PBev6KOcta2RsY+3i6GDk5JARMJK7PWcwM YYtJXLi3ng3EFhJYxCjxvbWki5ELyJ7IJLH//2uwIjYBI4mtJ6cxgtgiAhISv/qvMoIUMQt0 MEpMOv0GLCEsECpxrXsfO4jNIqAqMeViHxOIzSvgIXHnSScjxDYFiWNTv7KC2JwCnhJLH61g hNjsIdHZN5N1AiPvAkaGVYyiqQXJBcVJ6blGesWJucWleel6yfm5mxjB/n8mvYNxVYPFIUYB DkYlHt5tKx76C7EmlhVX5h5ilOBgVhLhLe8ACvGmJFZWpRblxxeV5qQWH2KU5mBREudtsr7g LySQnliSmp2aWpBaBJNl4uCUamBMDImwuKrEuHXKy7TM1M+Of1zOfdJbuGVX+aLFfu2bNqqx XZY/9Dvk+cvQzTtNe84I75dT+sp+m2tBfsE0iwczzgBhZExI/Ie5u7yLxCyNGU71Lb72KtBq AqufzZJ99gmTFlmLyZz7GxV2VGRXVX5w/RTZ3BMzfpfeevdg+Yvta4tuuz9bslKJpTgj0VCL uag4EQBG4lHv+wEAAA== X-TM-AS-MML: No X-Gm-Message-State: ALoCoQkPiuzvT5DftRiNM9PDt04osnBzYz4Dq7r5sJxi178VmWBD+zc9eq1whZAcTVSGUrky6JYx This patch modifies the pinmux settings of MMC and UART as per Exynos5250 Rev 1.0 Signed-off-by: Rajeshwari Shinde --- Chnages in V2: - None arch/arm/cpu/armv7/exynos/pinmux.c | 18 +++++++++--------- 1 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index d2b7d2c..7611c7a 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -40,8 +40,8 @@ static void exynos5_uart_config(int peripheral) count = 4; break; case PERIPH_ID_UART1: - bank = &gpio1->a0; - start = 4; + bank = &gpio1->d0; + start = 0; count = 4; break; case PERIPH_ID_UART2: @@ -66,25 +66,25 @@ static int exynos5_mmc_config(int peripheral, int flags) struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); struct s5p_gpio_bank *bank, *bank_ext; - int i; + int i, start; switch (peripheral) { case PERIPH_ID_SDMMC0: bank = &gpio1->c0; bank_ext = &gpio1->c1; + start = 0; break; case PERIPH_ID_SDMMC1: - bank = &gpio1->c1; + bank = &gpio1->c2; bank_ext = NULL; break; case PERIPH_ID_SDMMC2: - bank = &gpio1->c2; - bank_ext = &gpio1->c3; - break; - case PERIPH_ID_SDMMC3: bank = &gpio1->c3; bank_ext = NULL; break; + case PERIPH_ID_SDMMC3: + debug("SDMMC3 not supported yet"); + return -1; } if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) { debug("SDMMC device %d does not support 8bit mode", @@ -92,7 +92,7 @@ static int exynos5_mmc_config(int peripheral, int flags) return -1; } if (flags & PINMUX_FLAG_8BIT_MODE) { - for (i = 3; i <= 6; i++) { + for (i = start; i <= (start + 3); i++) { s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3)); s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP); s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);