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[203.254.224.33]) by mx.google.com with ESMTP id tg7si8308894pbc.39.2012.06.29.05.56.26; Fri, 29 Jun 2012 05:56:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.33 as permitted sender) client-ip=203.254.224.33; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.33 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm1.samsung.com (mailout3.samsung.com [203.254.224.33]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M6D00AI4QJYLLE0@mailout3.samsung.com>; Fri, 29 Jun 2012 21:56:20 +0900 (KST) X-AuditID: cbfee61a-b7f086d000000e64-f7-4feda5f4094d Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 7D.2E.03684.4F5ADEF4; Fri, 29 Jun 2012 21:56:20 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M6D00JE7QK7T260@mmp2.samsung.com>; Fri, 29 Jun 2012 21:56:20 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, alim.akhtar@samsung.com, dofmind@gmail.com, jh80.chung@samsung.com Subject: [PATCH 09/10 V4] EXYNOS5 : Modify pinnumx settings as per Exynos5250 Rev 1.0 Date: Fri, 29 Jun 2012 18:29:09 +0530 Message-id: <1340974750-19969-10-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1340974750-19969-1-git-send-email-rajeshwari.s@samsung.com> References: <1340974750-19969-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrJJMWRmVeSWpSXmKPExsVy+t9jQd0vS9/6G0zYY2LxcP1NFosph7+w ODB53Lm2hy2AMYrLJiU1J7MstUjfLoEr4++DXpaCcxIVXYc3sjQwXhDuYuTkkBAwkTh3uZcd whaTuHBvPVsXIxeHkMB0RokPZ9uYIZyJTBINcz8zg1SxCRhJbD05jRHEFhGQkPjVf5URpIhZ YBGjxN2eX2CjhAXCJVZO6WcBsVkEVCU2buoGs3kFPCWunJnFCLFOQeLY1K+sIDYnUPzJpiYw W0jAQ+LFm4usExh5FzAyrGIUTS1ILihOSs811CtOzC0uzUvXS87P3cQIDoBnUjsYVzZYHGIU 4GBU4uGtWPLWX4g1say4MvcQowQHs5II78PFQCHelMTKqtSi/Pii0pzU4kOM0hwsSuK8TdYX /IUE0hNLUrNTUwtSi2CyTBycUg2MhpMFOVqKWfp2LY3+2CQtN0FkQqhu/NxDlyRenP53dOrP rdd0ee2mmIozHL21yls9Np9nYcpN4wb5Mt/pLk1L8/gj9ZddPPdWTIn3b+TKLS/11Q/PmZ1l /l+jN3xHpWa5zpzDbR6ruPjzspd/KU/WF2jTlbquXi0dHBfOE2WxdpGq5ZngunQlluKMREMt 5qLiRABhT4Z9/AEAAA== X-TM-AS-MML: No X-Gm-Message-State: ALoCoQkEs1lzG2RGqasvlQ5wOvzNZiBjIcQ7Ktpq/FpkYDJXyOZUjm9Nm4hlSruXM4xSiczE/b62 This patch modifies the pinmux settings of MMC and UART as per Exynos5250 Rev 1.0. It also corrects the gpio offset calculations. Signed-off-by: Rajeshwari Shinde Acked-by: Joonyoung Shim --- Changes in V2: - None. Changes in V3: - Corrected the pinmux settings and offset calcuation of gpio banks. Changes in V4: - None arch/arm/cpu/armv7/exynos/pinmux.c | 22 +++++++++++++--------- arch/arm/include/asm/arch-exynos/gpio.h | 7 +++++-- 2 files changed, 18 insertions(+), 11 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index d2b7d2c..822410e 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -40,8 +40,8 @@ static void exynos5_uart_config(int peripheral) count = 4; break; case PERIPH_ID_UART1: - bank = &gpio1->a0; - start = 4; + bank = &gpio1->d0; + start = 0; count = 4; break; case PERIPH_ID_UART2: @@ -66,23 +66,27 @@ static int exynos5_mmc_config(int peripheral, int flags) struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); struct s5p_gpio_bank *bank, *bank_ext; - int i; + int i, start, gpio_func; switch (peripheral) { case PERIPH_ID_SDMMC0: bank = &gpio1->c0; bank_ext = &gpio1->c1; + start = 0; + gpio_func = GPIO_FUNC(0x2); break; case PERIPH_ID_SDMMC1: - bank = &gpio1->c1; + bank = &gpio1->c2; bank_ext = NULL; break; case PERIPH_ID_SDMMC2: - bank = &gpio1->c2; - bank_ext = &gpio1->c3; + bank = &gpio1->c3; + bank_ext = &gpio1->c4; + start = 3; + gpio_func = GPIO_FUNC(0x3); break; case PERIPH_ID_SDMMC3: - bank = &gpio1->c3; + bank = &gpio1->c4; bank_ext = NULL; break; } @@ -92,8 +96,8 @@ static int exynos5_mmc_config(int peripheral, int flags) return -1; } if (flags & PINMUX_FLAG_8BIT_MODE) { - for (i = 3; i <= 6; i++) { - s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3)); + for (i = start; i <= (start + 3); i++) { + s5p_gpio_cfg_pin(bank_ext, i, gpio_func); s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP); s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); } diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index 7a9bb90..97be4ea 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -100,7 +100,9 @@ struct exynos5_gpio_part1 { struct s5p_gpio_bank y4; struct s5p_gpio_bank y5; struct s5p_gpio_bank y6; - struct s5p_gpio_bank res1[0x980]; + struct s5p_gpio_bank res1[0x3]; + struct s5p_gpio_bank c4; + struct s5p_gpio_bank res2[0x48]; struct s5p_gpio_bank x0; struct s5p_gpio_bank x1; struct s5p_gpio_bank x2; @@ -122,9 +124,10 @@ struct exynos5_gpio_part2 { struct exynos5_gpio_part3 { struct s5p_gpio_bank v0; struct s5p_gpio_bank v1; + struct s5p_gpio_bank res1[0x1]; struct s5p_gpio_bank v2; struct s5p_gpio_bank v3; - struct s5p_gpio_bank res1[0x20]; + struct s5p_gpio_bank res2[0x1]; struct s5p_gpio_bank v4; };