From patchwork Thu Aug 2 07:25:04 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajeshwari Shinde X-Patchwork-Id: 10454 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 8BDA82402A for ; Thu, 2 Aug 2012 07:18:55 +0000 (UTC) Received: from mail-yw0-f52.google.com (mail-yw0-f52.google.com [209.85.213.52]) by fiordland.canonical.com (Postfix) with ESMTP id 5C1EBA18040 for ; Thu, 2 Aug 2012 07:18:55 +0000 (UTC) Received: by mail-yw0-f52.google.com with SMTP id p61so8252009yhp.11 for ; Thu, 02 Aug 2012 00:18:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:x-auditid :from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-brightmail-tracker:x-tm-as-mml:x-gm-message-state; bh=O6ETM+Vizi8Y116/ApJQXUbeetk2pOiGIRLPt4YjBgU=; b=O+MPm0yfzdOXv3/C+PN0WD0SF4IhlTsmDw1Kp29GkOtTNI+YqKlkx7XmWaJB5Y3dRA etcjzRrK6oa7AxgoaJwz7SRd3Vcsdi7Wu0f8QBCXH+P9SrGhKKKRnjqBluAmS3/nHvYL bxP13UqBnJKlNg4la8j0rQLZ+S2YM1/MCZP+y3yuiLnfE/8W5PzTUqUDFk6jpFagytN8 K5LT5f7MT0S6sO8Uzq8sWW4nj/jaZPaNeB6BX/4C0XBmcAdx0gRdigK6v4GFMCyG2cNm ilCYjbkPlWbWK6f+tfYdZyXQq53zmFqdNkGvuNzetTP8NBfBEXuYf7J1HUrIpKc1XQCS G97w== Received: by 10.50.149.134 with SMTP id ua6mr1857297igb.11.1343891934946; Thu, 02 Aug 2012 00:18:54 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.87.40 with SMTP id u8csp239552igz; Thu, 2 Aug 2012 00:18:54 -0700 (PDT) Received: by 10.43.43.194 with SMTP id ud2mr2452517icb.13.1343891934597; Thu, 02 Aug 2012 00:18:54 -0700 (PDT) Received: from mailout1.samsung.com (mailout1.samsung.com. [203.254.224.24]) by mx.google.com with ESMTP id m6si5768854oec.41.2012.08.02.00.18.54; Thu, 02 Aug 2012 00:18:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.24 as permitted sender) client-ip=203.254.224.24; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.24 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm2.samsung.com (mailout1.samsung.com [203.254.224.24]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M8400DV19MFQTO0@mailout1.samsung.com>; Thu, 02 Aug 2012 16:18:53 +0900 (KST) X-AuditID: cbfee61b-b7f566d000005c8a-ea-501a29dc37bf Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 33.D5.23690.CD92A105; Thu, 02 Aug 2012 16:18:53 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M840099U9N7OKD0@mmp1.samsung.com>; Thu, 02 Aug 2012 16:18:52 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, alim.akhtar@samsung.com, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, vapier@gentoo.org Subject: [PATCH 1/7 V4] EXYNOS5: Add pinmux support for SPI Date: Thu, 02 Aug 2012 12:55:04 +0530 Message-id: <1343892310-21018-2-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1343892310-21018-1-git-send-email-rajeshwari.s@samsung.com> References: <1343892310-21018-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrBJMWRmVeSWpSXmKPExsVy+t9jAd27mlIBBpOmslo8XH+TxWLK4S8s Dkwed67tYQtgjOKySUnNySxLLdK3S+DKaHiykrVgpljFlQm32BoY3wt2MXJySAiYSBw/38MG YYtJXLi3Hsjm4hASWMQo0T1zJxOEM5FJ4tDVF4wgVWwCRhJbT04Ds0UEJCR+9V9lBCliFuhg lDj8bQcTSEJYwFqi+9tmsLEsAqoSuydtZwexeQU8JDYdXccEsU5B4tjUr6wgNqeAp8TFOSuZ uxg5gLZ5SHx7nzeBkXcBI8MqRtHUguSC4qT0XCO94sTc4tK8dL3k/NxNjGD/P5PewbiqweIQ owAHoxIP78pSyQAh1sSy4srcQ4wSHMxKIrx3JKQChHhTEiurUovy44tKc1KLDzFKc7AoifOa eH/1FxJITyxJzU5NLUgtgskycXBKNTA2LFX+fdxj+ZElv4r+nvHduPtdjNcUPfftGYp3bVUU sm2nbNL58e7Mln0KHwM/VkyWCFr+LdNep7yh6xvveallixnWlc1lV1CU7+3y8U1ubtZVeNyQ Mf3Z/0s1f9qWW6ed4n354Nc7pusfzhrNjpkg861pfkpx5I71i6bob7m6/uOZqI9al+a+U2Ip zkg01GIuKk4EAAXPyAH7AQAA X-TM-AS-MML: No X-Gm-Message-State: ALoCoQnRAo+09/eXCE1CugeGakvN0xoWLEWvkgboAAsRtGuukNnz39J49AEDEjcsDFWcugEBc//8 This patch adds pinmux support for SPI channels Signed-off-by: Rajeshwari Shinde --- Changes in V2: - None. Changes in V3: - Removed the slave flag for SPI. Changes in V4: - Rebased on Mainline u-boot.git. arch/arm/cpu/armv7/exynos/pinmux.c | 51 ++++++++++++++++++++++++++++- arch/arm/include/asm/arch-exynos/periph.h | 5 +++ 2 files changed, 55 insertions(+), 1 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index d28f055..415d7fa 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -226,6 +226,49 @@ static void exynos5_i2c_config(int peripheral, int flags) } } +void exynos5_spi_config(int peripheral) +{ + int cfg = 0, pin = 0, i; + struct s5p_gpio_bank *bank = NULL; + struct exynos5_gpio_part1 *gpio1 = + (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); + struct exynos5_gpio_part2 *gpio2 = + (struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2(); + + switch (peripheral) { + case PERIPH_ID_SPI0: + bank = &gpio1->a2; + cfg = GPIO_FUNC(0x2); + pin = 0; + break; + case PERIPH_ID_SPI1: + bank = &gpio1->a2; + cfg = GPIO_FUNC(0x2); + pin = 4; + break; + case PERIPH_ID_SPI2: + bank = &gpio1->b1; + cfg = GPIO_FUNC(0x5); + pin = 1; + break; + case PERIPH_ID_SPI3: + bank = &gpio2->f1; + cfg = GPIO_FUNC(0x2); + pin = 0; + break; + case PERIPH_ID_SPI4: + for (i = 2; i < 4; i++) + s5p_gpio_cfg_pin(&gpio2->f0, i, GPIO_FUNC(0x4)); + for (i = 4; i < 6; i++) + s5p_gpio_cfg_pin(&gpio2->e0, i, GPIO_FUNC(0x4)); + break; + } + if (peripheral != PERIPH_ID_SPI4) { + for (i = pin; i < pin + 4; i++) + s5p_gpio_cfg_pin(bank, i, cfg); + } +} + static int exynos5_pinmux_config(int peripheral, int flags) { switch (peripheral) { @@ -253,11 +296,17 @@ static int exynos5_pinmux_config(int peripheral, int flags) case PERIPH_ID_I2C7: exynos5_i2c_config(peripheral, flags); break; + case PERIPH_ID_SPI0: + case PERIPH_ID_SPI1: + case PERIPH_ID_SPI2: + case PERIPH_ID_SPI3: + case PERIPH_ID_SPI4: + exynos5_spi_config(peripheral); + break; default: debug("%s: invalid peripheral %d", __func__, peripheral); return -1; } - return 0; } diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h index b861d7d..dafc3f3 100644 --- a/arch/arm/include/asm/arch-exynos/periph.h +++ b/arch/arm/include/asm/arch-exynos/periph.h @@ -43,6 +43,11 @@ enum periph_id { PERIPH_ID_SDMMC2, PERIPH_ID_SDMMC3, PERIPH_ID_SROMC, + PERIPH_ID_SPI0, + PERIPH_ID_SPI1, + PERIPH_ID_SPI2, + PERIPH_ID_SPI3, + PERIPH_ID_SPI4, PERIPH_ID_UART0, PERIPH_ID_UART1, PERIPH_ID_UART2,