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Mon, 06 Aug 2012 22:00:51 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, alim.akhtar@samsung.com, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org Subject: [PATCH 2/4] S5P: GPIO: Add GPIO pin numbering to driver Date: Mon, 06 Aug 2012 18:35:05 +0530 Message-id: <1344258307-18934-3-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1344258307-18934-1-git-send-email-rajeshwari.s@samsung.com> References: <1344258307-18934-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrOJMWRmVeSWpSXmKPExsVy+t9jAV3mA/IBBm+maVs8XH+TxWLK4S8s Dkwed67tYQtgjOKySUnNySxLLdK3S+DKuL/2JXtBn2rFo89tbA2M6+W6GDk5JARMJOZsncEE YYtJXLi3nq2LkYtDSGARo8Sjj1dYIZyJTBKvZi1gA6liEzCS2HpyGiOILSIgIfGr/yqQzcHB LFAqMWViHkhYWMBBorWvD2woi4CqxIeO/SwgNq+Ah8T544uZIZYpSByb+pUVxOYU8JQ4N2MT WI0QUM37/g+MExh5FzAyrGIUTS1ILihOSs811CtOzC0uzUvXS87P3cQI9v4zqR2MKxssDjEK cDAq8fDeNJAPEGJNLCuuzD3EKMHBrCTCW7MQKMSbklhZlVqUH19UmpNafIhRmoNFSZzX2Pur v5BAemJJanZqakFqEUyWiYNTqoFR5k5+D3/ZqUP/nzEIRjuH7c10uzXv7NOW7IbKezM727mz jl2R87oe6/s7doaC6J9rzbN7AhQ2V+85lj/reUynx0XpC4Gz99hNCF3/6f+9G01c0ttF2n/+ XpH3VkY5rrmtmi9tz/kJfooFSq8YHk55skZbb23UEfXamn8l0ZIuonFv/RvPPZ2kxFKckWio xVxUnAgAeztmH/oBAAA= X-TM-AS-MML: No X-Gm-Message-State: ALoCoQmBohHDgmdhjyYeq+b4gGZRHm/czVnpIt2pUPtKIKagKrMsav04ZzI2NAEn3l6pHCEin1kd API's for GPIO pin numbering support are added to the generic S5P gpio driver Signed-off-by: Leela Krishna Amudala Signed-off-by: Simon Glass Signed-off-by: Rajeshawari Shinde --- drivers/gpio/s5p_gpio.c | 158 +++++++++++++++++++++++++++++++++++++++++++++-- 1 files changed, 152 insertions(+), 6 deletions(-) diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c index 47f3213..5c051d4 100644 --- a/drivers/gpio/s5p_gpio.c +++ b/drivers/gpio/s5p_gpio.c @@ -142,20 +142,165 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode) writel(value, &bank->drv); } -struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio) + +int s5p_gpio_get_pin(unsigned gpio) { - int bank = gpio / GPIO_PER_BANK; - bank *= sizeof(struct s5p_gpio_bank); + return gpio % GPIO_PER_BANK; +} - return (struct s5p_gpio_bank *) (s5p_gpio_base(gpio) + bank); +#ifdef HAVE_GENERIC_GPIO +static struct s5p_gpio_bank *gpio_get_bank(unsigned int gpio) +{ + int bank_offset; + + if (gpio < GPIO_MAX_PORT_PART_1) { + bank_offset = gpio / GPIO_PER_BANK; + return (struct s5p_gpio_bank *) (EXYNOS5_GPIO_PART1_BASE + (bank_offset * + sizeof(struct s5p_gpio_bank))); + } else if (gpio < GPIO_MAX_PORT_PART_2) { + bank_offset = (gpio - GPIO_MAX_PORT_PART_1) / GPIO_PER_BANK; + return (struct s5p_gpio_bank *) (EXYNOS5_GPIO_PART2_BASE + (bank_offset * + sizeof(struct s5p_gpio_bank))); + } else if (gpio < GPIO_MAX_PORT_PART_3) { + bank_offset = (gpio - GPIO_MAX_PORT_PART_2) / GPIO_PER_BANK; + return (struct s5p_gpio_bank *) (EXYNOS5_GPIO_PART3_BASE + (bank_offset * + sizeof(struct s5p_gpio_bank))); + } + else + return (struct s5p_gpio_bank *) EXYNOS5_GPIO_PART4_BASE; + + return NULL; } -int s5p_gpio_get_pin(unsigned gpio) +void gpio_cfg_pin(int gpio, int cfg) { - return gpio % GPIO_PER_BANK; + unsigned int value; + struct s5p_gpio_bank *bank = gpio_get_bank(gpio); + + value = readl(&bank->con); + value &= ~CON_MASK(GPIO_BIT(gpio)); + value |= CON_SFR(GPIO_BIT(gpio), cfg); + writel(value, &bank->con); +} + +void gpio_set_pull(int gpio, int mode) +{ + unsigned int value; + struct s5p_gpio_bank *bank = gpio_get_bank(gpio); + + value = readl(&bank->pull); + value &= ~PULL_MASK(GPIO_BIT(gpio)); + + switch (mode) { + case GPIO_PULL_DOWN: + case GPIO_PULL_UP: + value |= PULL_MODE(GPIO_BIT(gpio), mode); + break; + default: + break; + } + + writel(value, &bank->pull); +} + +void gpio_set_drv(int gpio, int mode) +{ + unsigned int value; + struct s5p_gpio_bank *bank = gpio_get_bank(gpio); + + value = readl(&bank->drv); + value &= ~DRV_MASK(GPIO_BIT(gpio)); + + switch (mode) { + case GPIO_DRV_1X: + case GPIO_DRV_2X: + case GPIO_DRV_3X: + case GPIO_DRV_4X: + value |= DRV_SET(GPIO_BIT(gpio), mode); + break; + default: + return; + } + + writel(value, &bank->drv); } +void gpio_set_rate(int gpio, int mode) +{ + unsigned int value; + struct s5p_gpio_bank *bank = gpio_get_bank(gpio); + + value = readl(&bank->drv); + value &= ~RATE_MASK(GPIO_BIT(gpio)); + + switch (mode) { + case GPIO_DRV_FAST: + case GPIO_DRV_SLOW: + value |= RATE_SET(GPIO_BIT(gpio)); + break; + default: + return; + } + + writel(value, &bank->drv); +} + +int gpio_direction_input(unsigned gpio) +{ + gpio_cfg_pin(gpio, GPIO_INPUT); + + return 0; +} + +int gpio_direction_output(unsigned gpio, int value) +{ + unsigned int val; + struct s5p_gpio_bank *bank = gpio_get_bank(gpio); + + gpio_cfg_pin(gpio, GPIO_OUTPUT); + + val = readl(&bank->dat); + val &= ~DAT_MASK(GPIO_BIT(gpio)); + if (value) + val |= DAT_SET(GPIO_BIT(gpio)); + writel(val, &bank->dat); + + return 0; +} + +int gpio_get_value(unsigned gpio) +{ + unsigned int value; + struct s5p_gpio_bank *bank = gpio_get_bank(gpio); + + value = readl(&bank->dat); + return !!(value & DAT_MASK(GPIO_BIT(gpio))); +} + + +int gpio_set_value(unsigned gpio, int value) +{ + unsigned int val; + struct s5p_gpio_bank *bank = gpio_get_bank(gpio); + + val = readl(&bank->dat); + val &= ~DAT_MASK(GPIO_BIT(gpio)); + if (value) + val |= DAT_SET(GPIO_BIT(gpio)); + writel(val, &bank->dat); + + return 0; +} + +#else /* Common GPIO API */ +struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio) +{ + int bank = gpio / GPIO_PER_BANK; + bank *= sizeof(struct s5p_gpio_bank); + + return (struct s5p_gpio_bank *) (s5p_gpio_base(gpio) + bank); +} int gpio_request(unsigned gpio, const char *label) { @@ -194,3 +339,4 @@ int gpio_set_value(unsigned gpio, int value) return 0; } +#endif /* HAVE_GENERIC_GPIO */