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Wed, 17 Oct 2012 14:03:25 +0900 (KST) Received: from hatim-linux.sisodomain.com ([107.108.73.95]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MC000DANTZD3GA0@mmp1.samsung.com> for patches@linaro.org; Wed, 17 Oct 2012 14:03:25 +0900 (KST) From: Hatim Ali To: u-boot@lists.denx.de Cc: promsoft@gmail.com, patches@linaro.org Subject: [PATCH 1/6 V6] EXYNOS5: Add pinmux support for SPI Date: Wed, 17 Oct 2012 10:28:20 +0530 Message-id: <1350449905-10376-2-git-send-email-hatim.rv@samsung.com> X-Mailer: git-send-email 1.7.2.3 In-reply-to: <1350449905-10376-1-git-send-email-hatim.rv@samsung.com> References: <1350449905-10376-1-git-send-email-hatim.rv@samsung.com> DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrJLMWRmVeSWpSXmKPExsWyRsSkRlfWpi7A4NJ1U4sph7+wODB63Lm2 hy2AMYrLJiU1J7MstUjfLoEr4/qr8ywF38Urlu3+xN7AuF+4i5GTQ0LAROL8rr/sELaYxIV7 69m6GLk4hASWMkq83TGDBaZo/fUvzBCJRYwSy/a+ZQNJADlMErvXcoHYbAJqEutfd4LFRQQk JH71X2UEsZkFtCT2fJ0PFhcWsJZ43dIDFOfgYBFQlVjzqRzE5BVwkbixkw9ilYLEqxtrwe7h FHCV+HPxDli1EFDJnkY9kDCLgIDEt8mHWEDCEgKyEpsOgB0mIXCGTWLTyuNsEGMkJQ6uuMEy gVF4ASPDKkbR1ILkguKk9FxDveLE3OLSvHS95PzcTYzA8Dv975nUDsaVDRaHGAU4GJV4eD/M rg0QYk0sK67MPcQowcGsJMJr3ggU4k1JrKxKLcqPLyrNSS0+xOgDdMlEZinR5HxgbOSVxBsa m5ibGptaGhmZmZriEFYS5232SAkQEkhPLEnNTk0tSC2CGcfEwSnVwGh6I8eT69Ies4SghOUC W5ml+37Jea5/KHL53M41qqJHeavci+VuNnuIiDc3Hf8fWjmBc+OOBe8OOnN0za2JmpDNIr9o raRiksHZJ9NzRJ79iNN81t2XyOXY+uSMQsfCfQ8OZi2yMfn3/1mxovD+BKfVntbvrsQXCPAc 27d5i/p9e8nAArOHj5VYijMSDbWYi4oTAYkMQQxsAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupgkeLIzCtJLcpLzFFi42I5/e+xgK6sTV2AwZNjOhZTDn9hcWD0uHNt D1sAY1QDo01GamJKapFCal5yfkpmXrqtkndwvHO8qZmBoa6hpYW5kkJeYm6qrZKLT4CuW2YO 0FglhbLEnFKgUEBicbGSvh2mCaEhbroWMI0Rur4hQXA9RgZoIGENY8b1V+dZCr6LVyzb/Ym9 gXG/cBcjJ4eEgInE+utfmCFsMYkL99azdTFycQgJLGKUWLb3LRtIAshhkti9lgvEZhNQk1j/ uhMsLiIgIfGr/yojiM0soCWx5+t8sLiwgLXE65YeoDgHB4uAqsSaT+UgJq+Ai8SNnXwQqxQk Xt1Yyw5icwq4Svy5eAesWgioZE+j3gRG3gWMDKsYRVMLkguKk9JzDfWKE3OLS/PS9ZLzczcx goP7mdQOxpUNFocYBTgYlXh4P8yuDRBiTSwrrsw9xCjBwawkwmveCBTiTUmsrEotyo8vKs1J LT7E6AN00kRmKdHkfGDk5ZXEGxqbmJsam1qaWJiYWeIQVhLnbfZICRASSE8sSc1OTS1ILYIZ x8TBKdXAeJLhdAhvUdETphMPOtSVpi7blpa++tk20aDd7AkOq4K/X0jy/h8440MOg/0+jq0p qyxMvQ6eSOrMnLZ/36KIdwf/PVz2Tn/95GuCnN4NAk0pp+6o69hNFbHS6Lw/wdI+9fXElube cpPMvXucurvrkg7N+tQTX/1c6ooz10OXGnaBBcERtRcclFiKMxINtZiLihMBRfpqQ5sCAAA= X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQm5gF5o0ISeXNck+ozYWGpDWD6YdUV/PzoZA64Hn9+vP8k1Cd3cx+KuyHsyP8hdY49KOcXq From: Rajeshwari Shinde This patch adds pinmux support for SPI channels Signed-off-by: Rajeshwari Shinde Signed-off-by: Hatim Ali --- Changes since v4: Fixed minor nits suggested by Simon Glass Changes since v5: No change arch/arm/cpu/armv7/exynos/pinmux.c | 51 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/periph.h | 5 +++ 2 files changed, 56 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 5796d56..e01bef4 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -112,6 +112,7 @@ static int exynos5_mmc_config(int peripheral, int flags) s5p_gpio_set_pull(bank, i, GPIO_PULL_UP); s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); } + return 0; } @@ -230,6 +231,49 @@ static void exynos5_i2c_config(int peripheral, int flags) } } +void exynos5_spi_config(int peripheral) +{ + int cfg = 0, pin = 0, i; + struct s5p_gpio_bank *bank = NULL; + struct exynos5_gpio_part1 *gpio1 = + (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); + struct exynos5_gpio_part2 *gpio2 = + (struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2(); + + switch (peripheral) { + case PERIPH_ID_SPI0: + bank = &gpio1->a2; + cfg = GPIO_FUNC(0x2); + pin = 0; + break; + case PERIPH_ID_SPI1: + bank = &gpio1->a2; + cfg = GPIO_FUNC(0x2); + pin = 4; + break; + case PERIPH_ID_SPI2: + bank = &gpio1->b1; + cfg = GPIO_FUNC(0x5); + pin = 1; + break; + case PERIPH_ID_SPI3: + bank = &gpio2->f1; + cfg = GPIO_FUNC(0x2); + pin = 0; + break; + case PERIPH_ID_SPI4: + for (i = 2; i < 4; i++) + s5p_gpio_cfg_pin(&gpio2->f0, i, GPIO_FUNC(0x4)); + for (i = 4; i < 6; i++) + s5p_gpio_cfg_pin(&gpio2->e0, i, GPIO_FUNC(0x4)); + break; + } + if (peripheral != PERIPH_ID_SPI4) { + for (i = pin; i < pin + 4; i++) + s5p_gpio_cfg_pin(bank, i, cfg); + } +} + static int exynos5_pinmux_config(int peripheral, int flags) { switch (peripheral) { @@ -257,6 +301,13 @@ static int exynos5_pinmux_config(int peripheral, int flags) case PERIPH_ID_I2C7: exynos5_i2c_config(peripheral, flags); break; + case PERIPH_ID_SPI0: + case PERIPH_ID_SPI1: + case PERIPH_ID_SPI2: + case PERIPH_ID_SPI3: + case PERIPH_ID_SPI4: + exynos5_spi_config(peripheral); + break; default: debug("%s: invalid peripheral %d", __func__, peripheral); return -1; diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h index 082611c..4054fb6 100644 --- a/arch/arm/include/asm/arch-exynos/periph.h +++ b/arch/arm/include/asm/arch-exynos/periph.h @@ -44,6 +44,11 @@ enum periph_id { PERIPH_ID_SDMMC3, PERIPH_ID_SDMMC4, PERIPH_ID_SROMC, + PERIPH_ID_SPI0, + PERIPH_ID_SPI1, + PERIPH_ID_SPI2, + PERIPH_ID_SPI3, + PERIPH_ID_SPI4, PERIPH_ID_UART0, PERIPH_ID_UART1, PERIPH_ID_UART2,