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Date: Thu, 29 Nov 2012 13:42:56 +0530 Message-id: <1354176776-17407-1-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrJLMWRmVeSWpSXmKPExsWyRsSkWrdLfHuAwZbrlhYP199ksZhy+AuL A5PHnWt72AIYo7hsUlJzMstSi/TtErgyVrw9yF6wirvib8M6lgbGVZxdjJwcEgImEhO2X2aD sMUkLtxbD2RzcQgJLGWUWN1/gRmmaN26bywQiemMEt1L9jBDOBOZJB5O7wRrZxMwkth6choj iC0iICHxq/8qmM0sUCLx7Vs3K4gtLKAncfDgFxYQm0VAVWLhojvsXYwcHLwCHhI/l0dBLFOQ ODb1KytEiYDEt8mHWEBKJARkJTYdAFsrIXCETeL3nR/sEPWSEgdX3GCZwCi4gJFhFaNoakFy QXFSeq6hXnFibnFpXrpecn7uJkZgeJ3+90xqB+PKBotDjAIcjEo8vJsstwUIsSaWFVfmHmKU 4GBWEuHV/AMU4k1JrKxKLcqPLyrNSS0+xOgDdMlEZinR5Hxg6OeVxBsam5ibGptaGhmZmZri EFYS5232SAkQEkhPLEnNTk0tSC2CGcfEwSnVwGh24cbcvil9B05aFxy6JzF3+90vxyx+ZiVq T0zaJR10/OSm10v9Nhy2MX5Ul5/evHSdeuE0gZJdLWIiTz9+qBON+p95bbWkgs2TSUzG6xJ+ 5qe37susYanK6vudK7h5SeLKyXfnWdqJLlqxzYWxwbu9dvfMNRxu/8+q3f95Vd+r+tqS7Wdb vEuUWIozEg21mIuKEwGpa/wVXAIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrBLMWRmVeSWpSXmKPExsVy+t9jQd0u8e0BBk0P9Cwerr/JYjHl8BcW ByaPO9f2sAUwRjUw2mSkJqakFimk5iXnp2TmpdsqeQfHO8ebmhkY6hpaWpgrKeQl5qbaKrn4 BOi6ZeYAzVZSKEvMKQUKBSQWFyvp22GaEBripmsB0xih6xsSBNdjZIAGEtYwZqx4e5C9YBV3 xd+GdSwNjKs4uxg5OSQETCTWrfvGAmGLSVy4t56ti5GLQ0hgOqNE95I9zBDORCaJh9M72UCq 2ASMJLaenMYIYosISEj86r8KZjMLlEh8+9bNCmILC+hJHDz4BWwqi4CqxMJFd9i7GDk4eAU8 JH4uj4JYpiBxbOpX1gmM3AsYGVYxiqYWJBcUJ6XnGuoVJ+YWl+al6yXn525iBAfvM6kdjCsb LA4xCnAwKvHwbrLcFiDEmlhWXJl7iFGCg1lJhFfzD1CINyWxsiq1KD++qDQntfgQow/Q8onM UqLJ+cDIyiuJNzQ2MTc1NrU0sTAxs8QhrCTO2+yREiAkkJ5YkpqdmlqQWgQzjomDU6qB8ULZ BI/aqS0THV6/tNBJvHkw0vrbYV6Nhj3nYld2BmzL2bgmRJ9/F+f+9X2Zm1ZM7f6fdyNMM3XF 20u++yqEm7oufthzY/rRq//Dz1feSdX6sXC3/lL9Gou/y0vjsuexrTnQZbTx079QKcvb057z V085E1ng8n354+WBn+pWPpzwWP9gjNfMxElKLMUZiYZazEXFiQDid7VGiwIAAA== X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQlqODzLmUb/vpWlSXqMwDurww5xybWXQkJ6FjmWkhc6jsi9AkJw+e+qeTWFF/wmBdU4x87G This patch set adds L2 Cache Support to EXYNOS. Signed-off-by: Arun Mankuzhi Signed-off-by: Rajeshwari Shinde --- arch/arm/cpu/armv7/exynos/soc.c | 36 ++++++++++++++++++++++++++++++++++++ 1 files changed, 36 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/soc.c b/arch/arm/cpu/armv7/exynos/soc.c index ab65b8d..a45bbfb 100644 --- a/arch/arm/cpu/armv7/exynos/soc.c +++ b/arch/arm/cpu/armv7/exynos/soc.c @@ -23,6 +23,14 @@ #include #include +#include + +enum l2_cache_params { + CACHE_TAG_RAM_SETUP = (1<<9), + CACHE_DATA_RAM_SETUP = (1<<5), + CACHE_TAG_RAM_LATENCY = (2<<6), + CACHE_DATA_RAM_LATENCY = (2<<0) +}; void reset_cpu(ulong addr) { @@ -36,3 +44,31 @@ void enable_caches(void) dcache_enable(); } #endif + +#ifndef CONFIG_SYS_L2CACHE_OFF +/* + * Set L2 cache parameters + */ +static void exynos5_set_l2cache_params(void) +{ + unsigned int val = 0; + + asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r"(val)); + + val |= CACHE_TAG_RAM_SETUP | + CACHE_DATA_RAM_SETUP | + CACHE_TAG_RAM_LATENCY | + CACHE_DATA_RAM_LATENCY; + + asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val)); +} + +/* + * Sets L2 cache related parameters before enabling data cache + */ +void v7_outer_cache_enable(void) +{ + exynos5_set_l2cache_params(); +} +#endif +