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Mon, 17 Dec 2012 19:57:27 +0900 (KST) Received: from localhost.localdomain ([107.108.73.106]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MF600FNU92TR670@mmp2.samsung.com>; Mon, 17 Dec 2012 19:57:27 +0900 (KST) From: Amar To: u-boot@lists.denx.de Cc: patches@linaro.org, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, afleming@gmail.com, jh80.chung@samsung.com Subject: [PATCH 4/9] EXYNOS5: DWMMC: Added dt support for DWMMC Date: Mon, 17 Dec 2012 16:49:31 +0530 Message-id: <1355743176-12305-5-git-send-email-amarendra.xt@samsung.com> X-Mailer: git-send-email 1.7.0.4 In-reply-to: <1355743176-12305-1-git-send-email-amarendra.xt@samsung.com> References: <1355743176-12305-1-git-send-email-amarendra.xt@samsung.com> DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrELMWRmVeSWpSXmKPExsWyRsSkVnfGr3MBBmuvMVo8XH+TxWLK4S8s Dkwed67tYQtgjOKySUnNySxLLdK3S+DKWHh6CVvBfe2Kp53bmBsYG5W7GDk5JARMJG7OWsAK YYtJXLi3nq2LkYtDSGAWo8SVxt+MMEUHXnUzQSSmM0rMufiVFcJpZ5L4e+kZUIaDg01AVeLX YnuQBhEBCYlf/VcZQWqYBToYJXZM3Aw2SVjAXmL7th4mEJsFqH77s3nMIDavgIfEnUUvmSC2 KUi0LjvEDmJzCnhKfN79kAXEFgKq2bNrOjNEr4DEt8mHWED2SgjISmw6wAyyS0LgNpvEtId3 2SDmSEocXHGDZQKj8AJGhlWMoqkFyQXFSem5hnrFibnFpXnpesn5uZsYgQF5+t8zqR2MKxss DjEKcDAq8fAapZ4LEGJNLCuuzD3EKMHBrCTCK/0GKMSbklhZlVqUH19UmpNafIjRB+iSicxS osn5wGjJK4k3NDYxNzU2tTQyMjM1xSGsJM7b7JESICSQnliSmp2aWpBaBDOOiYNTqoHRjyf2 48PwCXHbdzddXrzqRGqY7A/rmx0RqhcTy80coiUueE+fyhXybt+K8xybXyR1L2TNrVlhuE+x YcXq/RJsd1anKtuUNIfY7dLtyv/PGJqR1fn2kj+vwAXRZNfgB5aeP53afsmqZy7I0DGd57vs nmneuc7gc7X8B8Jl3GuXJ670LfVK+qLEUpyRaKjFXFScCABPA4HXdQIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprIIsWRmVeSWpSXmKPExsVy+t9jQd3pv84FGNxYaGjxcP1NFosph7+w ODB53Lm2hy2AMaqB0SYjNTEltUghNS85PyUzL91WyTs43jne1MzAUNfQ0sJcSSEvMTfVVsnF J0DXLTMHaLaSQlliTilQKCCxuFhJ3w7ThNAQN10LmMYIXd+QILgeIwM0kLCGMWPh6SVsBfe1 K552bmNuYGxU7mLk5JAQMJE48KqbCcIWk7hwbz1bFyMXh5DAdEaJORe/skI47UwSfy89A6ri 4GATUJX4tdgepEFEQELiV/9VRpAaZoEORokdEzczgiSEBewltm/rAZvKAlS//dk8ZhCbV8BD 4s6il1DbFCRalx1iB7E5BTwlPu9+yAJiCwHV7Nk1nXkCI+8CRoZVjKKpBckFxUnpuYZ6xYm5 xaV56XrJ+bmbGMHh/kxqB+PKBotDjAIcjEo8vEap5wKEWBPLiitzDzFKcDArifBKvwEK8aYk VlalFuXHF5XmpBYfYvQBumois5Rocj4wFvNK4g2NTcxNjU0tTSxMzCxxCCuJ8zZ7pAQICaQn lqRmp6YWpBbBjGPi4JRqYNxq8W5F1WYHv9TalNvdK2Zn7wotE7PZ+nvPAwPOTadfJtTXrXxz Xi3lsZ+VnXjga94vqs2WrTfcnc/PCwpQCmAxSQpXD8u19fqZc8j/tVh1p9+0lr/nHtbFf1rZ 325ubS143D/BYm2QffRWX6k6h43a9f2/GmSmyEfo+nWoMyrLzjzHPcNLiaU4I9FQi7moOBEA Og3mi6QCAAA= X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQlTR/ozIrz2/zNqYM7V4peMPonhTIKgrwYVz+H/1S4ywaxSEefHL7qIScTnuBlrF3CTSUFS Signed-off-by: Amar --- arch/arm/include/asm/arch-exynos/dwmmc.h | 4 + drivers/mmc/exynos_dw_mmc.c | 117 ++++++++++++++++++++++++++++-- include/dwmmc.h | 4 + 3 files changed, 119 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h index 8acdf9b..92352df 100644 --- a/arch/arm/include/asm/arch-exynos/dwmmc.h +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h @@ -27,6 +27,9 @@ #define DWMCI_SET_DRV_CLK(x) ((x) << 16) #define DWMCI_SET_DIV_RATIO(x) ((x) << 24) +#ifdef CONFIG_OF_CONTROL +unsigned int exynos_dwmmc_init(const void *blob); +#else int exynos_dwmci_init(u32 regbase, int bus_width, int index); static inline unsigned int exynos_dwmmc_init(int index, int bus_width) @@ -34,3 +37,4 @@ static inline unsigned int exynos_dwmmc_init(int index, int bus_width) unsigned int base = samsung_get_base_mmc() + (0x10000 * index); return exynos_dwmci_init(base, bus_width, index); } +#endif diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index 72a31b7..3b3e3e5 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -19,23 +19,38 @@ */ #include -#include #include +#include +#include +#include #include #include +#include + +#define DWMMC_MAX_CH_NUM 4 +#define DWMMC_MAX_FREQ 52000000 +#define DWMMC_MIN_FREQ 400000 +#define DWMMC_MMC0_CLKSEL_VAL 0x03030001 +#define DWMMC_MMC2_CLKSEL_VAL 0x03020001 static char *EXYNOS_NAME = "EXYNOS DWMMC"; static void exynos_dwmci_clksel(struct dwmci_host *host) { - u32 val; - val = DWMCI_SET_SAMPLE_CLK(DWMCI_SHIFT_0) | - DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) | DWMCI_SET_DIV_RATIO(0); + dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val); +} - dwmci_writel(host, DWMCI_CLKSEL, val); +unsigned int exynos_dwmci_get_clk(int dev_index) +{ + return get_mmc_clk(dev_index); } +#ifdef CONFIG_OF_CONTROL +static int exynos_dwmci_init(u32 regbase, int bus_width, + int index, u32 *timing) +#else int exynos_dwmci_init(u32 regbase, int bus_width, int index) +#endif { struct dwmci_host *host = NULL; host = malloc(sizeof(struct dwmci_host)); @@ -44,14 +59,104 @@ int exynos_dwmci_init(u32 regbase, int bus_width, int index) return 1; } + /* set the clock divisor - clk_div_fsys for mmc */ + if (exynos5_mmc_set_clk_div(index)) { + debug("mmc clock div set failed\n"); + return -1; + } + host->name = EXYNOS_NAME; host->ioaddr = (void *)regbase; host->buswidth = bus_width; +#ifdef CONFIG_OF_CONTROL + host->clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) | + DWMCI_SET_DRV_CLK(timing[1]) | + DWMCI_SET_DIV_RATIO(timing[2])); +#else + if (0 == index) + host->clksel_val = DWMMC_MMC0_CLKSEL_VAL; + if (2 == index) + host->clksel_val = DWMMC_MMC2_CLKSEL_VAL; +#endif host->clksel = exynos_dwmci_clksel; host->dev_index = index; + host->mmc_clk = exynos_dwmci_get_clk; - add_dwmci(host, 52000000, 400000); + add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ); return 0; } +#ifdef CONFIG_OF_CONTROL +unsigned int exynos_dwmmc_init(const void *blob) +{ + u32 base; + int index, bus_width; + int node_list[DWMMC_MAX_CH_NUM]; + int err = 0; + int dev_id, flag; + u32 timing[3]; + int count, i; + + count = fdtdec_find_aliases_for_id(blob, "dwmmc", + COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list, + DWMMC_MAX_CH_NUM); + + for (i = 0; i < count; i++) { + int node = node_list[i]; + + if (node <= 0) + continue; + + /* config pinmux for each mmc channel */ + dev_id = pinmux_decode_periph_id(blob, node); + if (dev_id == PERIPH_ID_SDMMC0) + flag = PINMUX_FLAG_8BIT_MODE; + else + flag = PINMUX_FLAG_NONE; + + err = exynos_pinmux_config(dev_id, flag); + if (err) { + debug("DWMMC not configured\n"); + return err; + } + + /* Get the base address from the device node */ + base = fdtdec_get_addr(blob, node, "reg"); + if (!base) { + debug("DWMMC: Can't get base address\n"); + return -1; + } + + /* Get the channel index from the device node */ + index = fdtdec_get_int(blob, node, "index", 0); + if (index < 0) { + debug("DWMMC: Can't get channel index\n"); + return -1; + } + + /* Get the bus width from the device node */ + bus_width = fdtdec_get_int(blob, node, "bus-width", 0); + if (bus_width < 0) { + debug("DWMMC: Can't get bus-width\n"); + return -1; + } + + err = fdtdec_get_int_array(blob, node, "timing", + timing, 3); + if (err) { + debug("Can't get sdr-timings for divider\n"); + return -1; + } + + err = exynos_dwmci_init(base, bus_width, + index, timing); + if (err) { + debug("Can't do dwmci init\n"); + return -1; + } + } + + return 0; +} +#endif diff --git a/include/dwmmc.h b/include/dwmmc.h index c8b1d40..4a42849 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -123,6 +123,9 @@ #define MSIZE(x) ((x) << 28) #define RX_WMARK(x) ((x) << 16) #define TX_WMARK(x) (x) +#define RX_WMARK_SHIFT 16 +#define RX_WMARK_MASK (0xfff << RX_WMARK_SHIFT) + #define DWMCI_IDMAC_OWN (1 << 31) #define DWMCI_IDMAC_CH (1 << 4) @@ -144,6 +147,7 @@ struct dwmci_host { unsigned int bus_hz; int dev_index; int buswidth; + u32 clksel_val; u32 fifoth_val; struct mmc *mmc;