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[203.254.224.24]) by mx.google.com with ESMTP id ks7si48449254pbc.334.2013.01.04.01.12.12; Fri, 04 Jan 2013 01:12:13 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of amarendra.xt@samsung.com designates 203.254.224.24 as permitted sender) client-ip=203.254.224.24; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of amarendra.xt@samsung.com designates 203.254.224.24 as permitted sender) smtp.mail=amarendra.xt@samsung.com Received: from epcpsbgm1.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MG300AEHG7XGLC0@mailout1.samsung.com>; Fri, 04 Jan 2013 18:12:12 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.123]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id C2.60.01231.CEC96E05; Fri, 04 Jan 2013 18:12:12 +0900 (KST) X-AuditID: cbfee61a-b7fa66d0000004cf-e7-50e69cec8a3e Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id D1.60.01231.CEC96E05; Fri, 04 Jan 2013 18:12:12 +0900 (KST) Received: from chrome-ubuntu.sisodomain.com ([107.108.73.106]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MG30081AG7XXLA0@mmp1.samsung.com>; Fri, 04 Jan 2013 18:12:12 +0900 (KST) From: Amar To: u-boot@lists.denx.de, jh80.chung@samsung.com Cc: patches@linaro.org, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, afleming@gmail.com Subject: [PATCH V4 5/9] EXYNOS5: DWMMC: API to set mmc clock divisor Date: Fri, 04 Jan 2013 04:34:06 -0500 Message-id: <1357292050-12137-6-git-send-email-amarendra.xt@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1357292050-12137-1-git-send-email-amarendra.xt@samsung.com> References: <1357292050-12137-1-git-send-email-amarendra.xt@samsung.com> DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrDLMWRmVeSWpSXmKPExsWyRsSkWvfNnGcBBqcmqlk8XH+TxWLK4S8s Dkwed67tYQtgjOKySUnNySxLLdK3S+DKuL3iMHPBIf6KZfeWMTUwPuLpYuTgkBAwkdg1X76L kRPIFJO4cG89G4gtJLCUUeL8HTGIuInEraudzF2MXEDxRYwSL+avYoJwepkkeu/tYwQZxCag KvFrsT1Ig4iAgcT0J9tZQcLMAgUSz3aDzREWcJFoWDmVCcRmAaq+/eAeK4jNK+Ah8f11DzPE LjmJD3sesYO0cgp4Smy6IgJiCgGVXD1UAtEpIPFt8iEWiONlJTYdADtMQuA2m8TvU2egpkhK HFxxg2UCo/ACRoZVjKKpBckFxUnpuYZ6xYm5xaV56XrJ+bmbGIFBePrfM6kdjCsbLA4xCnAw KvHwWt55GiDEmlhWXJl7iFGCg1lJhPez9rMAId6UxMqq1KL8+KLSnNTiQ4w+QJdMZJYSTc4H RkheSbyhsYm5qbGppZGRmakpDmElcV7GU08ChATSE0tSs1NTC1KLYMYxcXBKNTDGxkf6yFxp 5jBtFrp+gCvWJupd59x7E1RKu579WHghYqGNCoOuIOfqk8ttlJatONwkuX3bjfnl2k0KRxn+ pz1RVfhTrMukLX9VwHh1qMGTVLebsyqSvX3PcpkHd8dNczCqWc08u4Z98bnsPrOzLz9d/VZv /HPildPclx7nTJyS+FzOa91lUxElluKMREMt5qLiRACHC3gXbwIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuplkeLIzCtJLcpLzFFi42I5/e+xgO6bOc8CDHZdFLV4uP4mi8WUw19Y HJg87lzbwxbAGNXAaJORmpiSWqSQmpecn5KZl26r5B0c7xxvamZgqGtoaWGupJCXmJtqq+Ti E6DrlpkDNFtJoSwxpxQoFJBYXKykb4dpQmiIm64FTGOErm9IEFyPkQEaSFjDmHF7xWHmgkP8 FcvuLWNqYHzE08XIySEhYCJx62onM4QtJnHh3nq2LkYuDiGBRYwSL+avYoJwepkkeu/tY+xi 5OBgE1CV+LXYHqRBRMBAYvqT7awgYWaBAolnu8VAwsICLhINK6cygdgsQNW3H9xjBbF5BTwk vr/ugdolJ/FhzyN2kFZOAU+JTVdEQEwhoJKrh0omMPIuYGRYxSiaWpBcUJyUnmuoV5yYW1ya l66XnJ+7iREc5s+kdjCubLA4xCjAwajEw2t552mAEGtiWXFl7iFGCQ5mJRHez9rPAoR4UxIr q1KL8uOLSnNSiw8x+gDdNJFZSjQ5HxiDeSXxhsYm5qbGppYmFiZmljiElcR5GU89CRASSE8s Sc1OTS1ILYIZx8TBKdXAuMxdMuvG/rbzviLb30ky+Kw6yrb+0etZFsZbXStT+6d8V16SW/09 1fHQIl5jNnO+2SrPu9eGhq259X/+S9+mNxc/SHN4Z32yP/N/jaZR7lQ+9edMy++/fxNuL3Cp MmC1+p6eO4GRhfPXbX4jIWTOVbJaej5j0yNTk/RPMr4aK3qt5ln9XHx2gRJLcUaioRZzUXEi AOtjvXegAgAA X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQnWQJIp/d1BMHAHqz8bowosz0tDma9xNyPZA6WSB81njGANGC+6UMuP1rMbwnIhvkLqUmcM This API computes the divisor value based on MPLL clock and writes it into the FSYS1 register. Changes from V1: 1)Updated the function exynos5_mmc_set_clk_div() to receive 'device_i'd as input parameter instead of 'index'. Changes from V2: 1)Updation of commit message and resubmition of proper patch set. Changes from V3: 1)Removed the new API exynos5_mmc_set_clk_div() from clock.c, because existing API set_mmc_clk() can be used to set mmc clock. Signed-off-by: Amar --- arch/arm/cpu/armv7/exynos/clock.c | 4 ++-- arch/arm/include/asm/arch-exynos/clk.h | 3 +++ 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 973b84e..89574ba 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -490,7 +490,7 @@ static unsigned long exynos4_get_mmc_clk(int dev_index) (struct exynos4_clock *)samsung_get_base_clock(); unsigned long uclk, sclk; unsigned int sel, ratio, pre_ratio; - int shift; + int shift = 0; sel = readl(&clk->src_fsys); sel = (sel >> (dev_index << 2)) & 0xf; @@ -539,7 +539,7 @@ static unsigned long exynos5_get_mmc_clk(int dev_index) (struct exynos5_clock *)samsung_get_base_clock(); unsigned long uclk, sclk; unsigned int sel, ratio, pre_ratio; - int shift; + int shift = 0; sel = readl(&clk->src_fsys); sel = (sel >> (dev_index << 2)) & 0xf; diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index 1935b0b..a4d5b4e 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -29,6 +29,9 @@ #define VPLL 4 #define BPLL 5 +#define FSYS1_MMC0_DIV_MASK 0xff0f +#define FSYS1_MMC0_DIV_VAL 0x0701 + unsigned long get_pll_clk(int pllreg); unsigned long get_arm_clk(void); unsigned long get_i2c_clk(void);