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[203.254.224.24]) by mx.google.com with ESMTP id gl1si21747952pac.235.2013.03.27.03.21.47; Wed, 27 Mar 2013 03:21:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.24 as permitted sender) client-ip=203.254.224.24; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.24 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgr4.samsung.com (u144.gpu120.samsung.co.kr [203.254.230.144]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MKB00GKZE40ZGJ0@mailout1.samsung.com>; Wed, 27 Mar 2013 19:21:47 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.123]) by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id 18.99.02019.A38C2515; Wed, 27 Mar 2013 19:21:47 +0900 (KST) X-AuditID: cbfee690-b7f656d0000007e3-b4-5152c83af98c Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 71.9A.13494.A38C2515; Wed, 27 Mar 2013 19:21:46 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MKB0096CE433Z90@mmp1.samsung.com>; Wed, 27 Mar 2013 19:21:46 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org Subject: [PATCH] EXYNOS: SPL: Add a custom spi copy function Date: Wed, 27 Mar 2013 15:58:20 +0530 Message-id: <1364380100-9983-1-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrILMWRmVeSWpSXmKPExsWyRsSkWtf6RFCgwfmjzBYP199kseg40sJo MeXwFxaLb1u2MVq83dvJ7sDqMbvhIovHnWt72DzO3tnB6NG3ZRVjAEsUl01Kak5mWWqRvl0C V8bxA/3sBWetKyZPa2drYHxr0MXIySEhYCLxZPsSNghbTOLCvfVANheHkMBSRondPRcYYYo6 zl1lgkgsYpTo2PIFqmoik8SkbVNYQKrYBIwktp6cBtYhIiAh8av/KpjNLBAj8Xr/D7AVwgI2 Er+eHWYCsVkEVCWOrZrBCmLzCrhLPN70mx1im4LEsalfWUEWSAi8ZpOY0LqHGaJBQOLb5ENA yziAErISmw4wQ9RLShxccYNlAqPgAkaGVYyiqQXJBcVJ6UUmesWJucWleel6yfm5mxiBwXn6 37MJOxjvHbA+xJgMNG4is5Rocj4wuPNK4g2NzYwsTE1MjY3MLc1IE1YS51VvsQ4UEkhPLEnN Tk0tSC2KLyrNSS0+xMjEwSnVwFi1lHHrZbfJacxF2j+FvisHnHvlufHfqw25TNPYOqesX7Hs Zvb8lpunIqcfUz7Sdrtj+4NXUw5+Ng7hs/Ay+GwZruv9wbB38zelSZwnp+p5XFmns+yd4Nm1 pV8STA/LX1G7kLPOfsdTU/P09f1H2Ht2ss+sPx7V+Svz3CeHy93pE86d2si/YouKEktxRqKh FnNRcSIAT0jXqWQCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrHIsWRmVeSWpSXmKPExsVy+t9jAV2rE0GBBqsazS0err/JYtFxpIXR YsrhLywW37ZsY7R4u7eT3YHVY3bDRRaPO9f2sHmcvbOD0aNvyyrGAJaoBkabjNTElNQihdS8 5PyUzLx0WyXv4HjneFMzA0NdQ0sLcyWFvMTcVFslF58AXbfMHKDNSgpliTmlQKGAxOJiJX07 TBNCQ9x0LWAaI3R9Q4LgeowM0EDCGsaM4wf62QvOWldMntbO1sD41qCLkZNDQsBEouPcVSYI W0ziwr31bF2MXBxCAosYJTq2fIFyJjJJTNo2hQWkik3ASGLryWmMILaIgITEr/6rYDazQIzE 6/0/2EBsYQEbiV/PDoNNZRFQlTi2agYriM0r4C7xeNNvdohtChLHpn5lncDIvYCRYRWjaGpB ckFxUnqukV5xYm5xaV66XnJ+7iZGcOg/k97BuKrB4hCjAAejEg+vw7/AQCHWxLLiytxDjBIc zEoivEYHggKFeFMSK6tSi/Lji0pzUosPMSYDbZ/ILCWanA+My7ySeENjE3NTY1NLEwsTM0vS hJXEeQ+2WgcKCaQnlqRmp6YWpBbBbGHi4JRqYFxQK1lctm7fHsPNblGrQriSNr29a7Fe6cP5 HXcYFt/wrE/xW+YgyxlfGTGtJtnYdW9bcdiBj2Z/zCe8MZ6yuMckdm+QQ9oLA+X1phuNk1P9 hW9p7tT4nCMnFqZslhDip5Y0kWlj0Rn2Szc6GOuX7Tbuf/5b4zxXhuIZpeL7V626bmeEGp7e rsRSnJFoqMVcVJwIAKVul+/BAgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQkPUmTaXNotHs1rHMORiK7410oT9zMyeaI2zdUxBMLbAYGFnMZFNgKNKxrER0U1X7pYDQc+ This CL implements a custom spi_copy funtion to copy u-boot from SF to RAM. This is faster then iROM spi_copy funtion as this runs spi at 50Mhz and also in WORD mode of operation. Changed a printf in pimux.c to debug just to avoid the the compilation error in SPL. Removed the enum for boot mode from spl_boot.c as it was already define in spl.h Signed-off-by: Alim Akhtar Signed-off-by: Tom Wai-Hong Tam Signe-off-by: Rajeshwari Shinde --- arch/arm/cpu/armv7/exynos/pinmux.c | 2 +- arch/arm/include/asm/arch-exynos/spi.h | 2 + board/samsung/smdk5250/spl_boot.c | 126 +++++++++++++++++++++++++++++--- include/configs/exynos5250-dt.h | 3 + spl/Makefile | 4 + 5 files changed, 124 insertions(+), 13 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 1e7d14c..445f6fa 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -399,7 +399,7 @@ static int exynos4_pinmux_config(int peripheral, int flags) case PERIPH_ID_SDMMC1: case PERIPH_ID_SDMMC3: case PERIPH_ID_SDMMC4: - printf("SDMMC device %d not implemented\n", peripheral); + debug("SDMMC device %d not implemented\n", peripheral); return -1; default: debug("%s: invalid peripheral %d", __func__, peripheral); diff --git a/arch/arm/include/asm/arch-exynos/spi.h b/arch/arm/include/asm/arch-exynos/spi.h index e67ad27..3430ac1 100644 --- a/arch/arm/include/asm/arch-exynos/spi.h +++ b/arch/arm/include/asm/arch-exynos/spi.h @@ -43,6 +43,8 @@ struct exynos_spi { #define SPI_TIMEOUT_MS 10 +#define SF_READ_DATA_CMD 0x3 + /* SPI_CHCFG */ #define SPI_CH_HS_EN (1 << 6) #define SPI_CH_RST (1 << 5) diff --git a/board/samsung/smdk5250/spl_boot.c b/board/samsung/smdk5250/spl_boot.c index d8f3c1e..9e99512 100644 --- a/board/samsung/smdk5250/spl_boot.c +++ b/board/samsung/smdk5250/spl_boot.c @@ -22,16 +22,119 @@ #include #include +#include +#include +#include +#include +#include +#include -enum boot_mode { - BOOT_MODE_MMC = 4, - BOOT_MODE_SERIAL = 20, - /* Boot based on Operating Mode pin settings */ - BOOT_MODE_OM = 32, - BOOT_MODE_USB, /* Boot using USB download */ -}; +static void spi_rx_tx(struct exynos_spi *regs, int todo, + void *dinp, void const *doutp, int i) +{ + uint *rxp = (uint *)(dinp + (i * (32 * 1024))); + int rx_lvl, tx_lvl; + uint out_bytes, in_bytes; + + out_bytes = in_bytes = todo; + setbits_le32(®s->ch_cfg, SPI_CH_RST); + clrbits_le32(®s->ch_cfg, SPI_CH_RST); + writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, ®s->pkt_cnt); + + while (in_bytes) { + uint32_t spi_sts; + int temp; + + spi_sts = readl(®s->spi_sts); + rx_lvl = ((spi_sts >> 15) & 0x7f); + tx_lvl = ((spi_sts >> 6) & 0x7f); + while (tx_lvl < 32 && out_bytes) { + temp = 0xffffffff; + writel(temp, ®s->tx_data); + out_bytes -= 4; + tx_lvl += 4; + } + while (rx_lvl >= 4 && in_bytes) { + temp = readl(®s->rx_data); + if (rxp) + *rxp++ = temp; + in_bytes -= 4; + rx_lvl -= 4; + } + } +} + +/** + * Copy uboot from spi flash to RAM + * + * @parma uboot_size size of u-boot to copy + * @param uboot_addr address of u-boot to copy + */ +static void exynos_spi_copy(unsigned int uboot_size, unsigned int uboot_addr) +{ + int upto, todo; + int i; + struct exynos_spi *regs = (struct exynos_spi *)CONFIG_ENV_SPI_BASE; + + set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ + /* set the spi1 GPIO */ + exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE); + + /* set pktcnt and enable it */ + writel(4 | SPI_PACKET_CNT_EN, ®s->pkt_cnt); + /* set FB_CLK_SEL */ + writel(SPI_FB_DELAY_180, ®s->fb_clk); + /* set CH_WIDTH and BUS_WIDTH as word */ + setbits_le32(®s->mode_cfg, SPI_MODE_CH_WIDTH_WORD | + SPI_MODE_BUS_WIDTH_WORD); + clrbits_le32(®s->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */ + + /* clear rx and tx channel if set priveously */ + clrbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); - typedef u32 (*spi_copy_func_t)(u32 offset, u32 nblock, u32 dst); + setbits_le32(®s->swap_cfg, SPI_RX_SWAP_EN | + SPI_RX_BYTE_SWAP | + SPI_RX_HWORD_SWAP); + + /* do a soft reset */ + setbits_le32(®s->ch_cfg, SPI_CH_RST); + clrbits_le32(®s->ch_cfg, SPI_CH_RST); + + /* now set rx and tx channel ON */ + setbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN); + clrbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */ + + /* Send read instruction (0x3h) followed by a 24 bit addr */ + writel((SF_READ_DATA_CMD << 24) | SPI_FLASH_UBOOT_POS, ®s->tx_data); + + /* waiting for TX done */ + while (!(readl(®s->spi_sts) & SPI_ST_TX_DONE)) + ; + + for (upto = 0, i = 0; upto < uboot_size; upto += todo, i++) { + todo = min(uboot_size - upto, (1 << 15)); + spi_rx_tx(regs, todo, (void *)(uboot_addr), + (void *)(SPI_FLASH_UBOOT_POS), i); + } + + setbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */ + + /* + * Let put controller mode to BYTE as + * SPI driver does not support WORD mode yet + */ + clrbits_le32(®s->mode_cfg, SPI_MODE_CH_WIDTH_WORD | + SPI_MODE_BUS_WIDTH_WORD); + writel(0, ®s->swap_cfg); + + /* + * Flush spi tx, rx fifos and reset the SPI controller + * and clear rx/tx channel + */ + clrsetbits_le32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST); + clrbits_le32(®s->ch_cfg, SPI_CH_RST); + clrbits_le32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON); +} /* * Copy U-boot from mmc to RAM: @@ -40,17 +143,16 @@ enum boot_mode { */ void copy_uboot_to_ram(void) { - spi_copy_func_t spi_copy; enum boot_mode bootmode; u32 (*copy_bl2)(u32, u32, u32); + struct spl_machine_param *param = spl_get_machine_params(); bootmode = readl(EXYNOS5_POWER_BASE) & OM_STAT; switch (bootmode) { case BOOT_MODE_SERIAL: - spi_copy = *(spi_copy_func_t *)EXYNOS_COPY_SPI_FNPTR_ADDR; - spi_copy(SPI_FLASH_UBOOT_POS, CONFIG_BL2_SIZE, - CONFIG_SYS_TEXT_BASE); + /* let us our own function to copy u-boot from SF */ + exynos_spi_copy(param->uboot_size, CONFIG_SYS_TEXT_BASE); break; case BOOT_MODE_MMC: copy_bl2 = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR; diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index 3d5b609..1910df8 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -135,6 +135,8 @@ /* MMC SPL */ #define CONFIG_SPL +#define CONFIG_SPL_GPIO_SUPPORT + #define COPY_BL2_FNPTR_ADDR 0x02020030 /* specific .lds file */ @@ -288,6 +290,7 @@ #define CONFIG_ENV_SPI_MODE SPI_MODE_0 #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE #define CONFIG_ENV_SPI_BUS 1 +#define CONFIG_ENV_SPI_BASE 0x12D30000 #define CONFIG_ENV_SPI_MAX_HZ 50000000 #endif diff --git a/spl/Makefile b/spl/Makefile index 101d478..0f5efc2 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -92,6 +92,10 @@ LIBS-y += arch/$(ARCH)/cpu/tegra-common/libcputegra-common.o LIBS-y += $(CPUDIR)/tegra-common/libtegra-common.o endif +ifneq ($(CONFIG_EXYNOS4)$(CONFIG_EXYNOS5),) +LIBS-y += $(CPUDIR)/s5p-common/libs5p-common.o +endif + # Add GCC lib ifeq ("$(USE_PRIVATE_LIBGCC)", "yes") PLATFORM_LIBGCC = $(SPLTREE)/arch/$(ARCH)/lib/libgcc.o