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[203.254.224.34]) by mx.google.com with ESMTP id ox10si6374593pbb.151.2013.04.03.06.52.30; Wed, 03 Apr 2013 06:52:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of amarendra.xt@samsung.com designates 203.254.224.34 as permitted sender) client-ip=203.254.224.34; Received: from epcpsbgr1.samsung.com (u141.gpu120.samsung.co.kr [203.254.230.141]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MKO00G6IMI5TWL0@mailout4.samsung.com>; Wed, 03 Apr 2013 22:51:41 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.126]) by epcpsbgr1.samsung.com (EPCPMTA) with SMTP id 1A.59.20872.DE33C515; Wed, 03 Apr 2013 22:51:41 +0900 (KST) X-AuditID: cbfee68d-b7f786d000005188-26-515c33edb036 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id CE.CE.17838.DE33C515; Wed, 03 Apr 2013 22:51:41 +0900 (KST) Received: from chrome-ubuntu.sisodomain.com ([107.108.73.106]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MKO00KW6MDEHT20@mmp2.samsung.com>; Wed, 03 Apr 2013 22:51:41 +0900 (KST) From: Amar To: u-boot@lists.denx.de, mk7.kang@samsung.com Cc: patches@linaro.org, sjg@chromium.org, chander.kashyap@linaro.org, afleming@gmail.com, jh80.chung@samsung.com, u-boot-review@google.com Subject: [PATCH V8 4/9] EXYNOS5: DWMMC: Added FDT support for DWMMC Date: Wed, 03 Apr 2013 10:08:28 -0400 Message-id: <1364998113-13428-5-git-send-email-amarendra.xt@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1364998113-13428-1-git-send-email-amarendra.xt@samsung.com> References: <1364998113-13428-1-git-send-email-amarendra.xt@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrPLMWRmVeSWpSXmKPExsWyRsSkTvetcUygwe5VYhY3rv9ks3i4/iaL xY1fbawWHUdaGC2mHP7CYvFtyzZGi+WvN7JbvN3bye7A4TG74SKLx85Zd9k9Fmwq9bhzbQ+b x9k7Oxg9+rasYgxgi+KySUnNySxLLdK3S+DKOHF1KWPBL5uKyWt+sjcwTjPsYuTgkBAwkdj4 rLiLkRPIFJO4cG89WxcjF4eQwFJGid8PFzDD1JxfYQARn84o8fL+F3YIp5dJovtnBxtIEZuA qsSvxfYgg0QE9CTmTXoHNohZoIdRYu/Sq0wgCWEBZ4muizvBbBag+lXPP7OB2LwCHhKfJjay QlwhJ/FhzyN2EJtTwFPi/bwdYPVCQDV3jj5kBRkqIbCOXeL09KksEIMEJL5NPsQCcamsxKYD zBBzJCUOrrjBMoFReAEjwypG0dSC5ILipPQiQ73ixNzi0rx0veT83E2MwMA//e9Z7w7G2wes DzEmA42byCwlmpwPjJy8knhDYzMjC1MTU2Mjc0sz0oSVxHnVWqwDhQTSE0tSs1NTC1KL4otK c1KLDzEycXBKNTCKT2Dh+3Z41xmdZkkLoQuubsFpCzwTDHKstPj+PfD0iG5uredRjVZ7fKPi p/niTXNDrszZv8Rvn/3VoO0HCm0MVgqsCE76erVk9Rs3a+47xdIiH44/KH24Zd3CvHsW9S/2 WtaFuFalL/nyTfjcU2PmrYw+xTn7MvPND/6eyW4+c+mnie5RbhuUWIozEg21mIuKEwFI96E7 kgIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrLIsWRmVeSWpSXmKPExsVy+t9jQd23xjGBBnvPcVvcuP6TzeLh+pss Fjd+tbFadBxpYbSYcvgLi8W3LdsYLZa/3shu8XZvJ7sDh8fshossHjtn3WX3WLCp1OPOtT1s Hmfv7GD06NuyijGALaqB0SYjNTEltUghNS85PyUzL91WyTs43jne1MzAUNfQ0sJcSSEvMTfV VsnFJ0DXLTMH6CIlhbLEnFKgUEBicbGSvh2mCaEhbroWMI0Rur4hQXA9RgZoIGENY8aJq0sZ C37ZVExe85O9gXGaYRcjB4eEgInE+RUGXYycQKaYxIV769m6GLk4hASmM0q8vP+FHcLpZZLo /tnBBtLAJqAq8WuxPUiDiICexLxJ78AamAV6GCX2Lr3KBJIQFnCW6Lq4E8xmAapf9fwzG4jN K+Ah8WliIyvENjmJD3sesYPYnAKeEu/n7QCrFwKquXP0IesERt4FjAyrGEVTC5ILipPScw31 ihNzi0vz0vWS83M3MYIj65nUDsaVDRaHGAU4GJV4eE98iQoUYk0sK67MPcQowcGsJMLLeTw6 UIg3JbGyKrUoP76oNCe1+BBjMtBVE5mlRJPzgVGfVxJvaGxibmpsamliYWJmSZqwkjjvgVbr QCGB9MSS1OzU1ILUIpgtTBycUg2M2mUdF7ubD7gn7jF/2DlJ3jPYa6uk4JoYuYDVqdedF577 fu1mpHLpOcv/n/4e4p0ctu+UM4Pd1JZVy3atO/4tQeJqsLJj1nVf3mNq7A6nnL1dbyX5ZE8W MOF9lbTy+o6nF8xlOR+9NlrItiz3sU7A8bYK1ulnkltrdrDnsnSx7mTfzLLN7bmtEktxRqKh FnNRcSIAKliwMPACAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQkjIluw1YSkYDy3ZZnrK3Prm0Yb6kYm+88Yz69WiAN3xfTZFlTAll93jH8/fKlqNKGMytyx X-Original-Sender: patch@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.175 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This patch adds FDT support for DWMMC, by reading the DWMMC node data from the device tree and initialising DWMMC channels as per data obtained from the node. Signed-off-by: Vivek Gautam Signed-off-by: Amar Acked-by: Simon Glass --- Changes since V1: 1)Updated code to have same signature for the function exynos_dwmci_init() for both FDT and non-FDT versions. 2)Updated code to pass device_id parameter to the function exynos5_mmc_set_clk_div() instead of index. 3)Updated code to decode the value of "samsung,width" from FDT. 4)Channel index is computed instead of getting from FDT. Changes since V2: 1)Updation of commit message and resubmition of proper patch set. Changes since V3: 1)Replaced the new function exynos5_mmc_set_clk_div() with the existing function set_mmc_clk(). set_mmc_clk() will do the purpose. 2)Computation of FSYS block clock divisor (pre-ratio) is added. Changes since V4: 1)Replaced "unsigned int exynos_dwmmc_init(int index, int bus_width)" with int exynos_dwmci_add_port(int, u32, inth, u32) i)exynos_dwmmc_add_port() will be used by non-FDT boards. ii)In FDT case, exynos_dwmmc_init(const void *blob) will use exynos_dwmmc_add_port() for every channel enabled in device node. 2)Changed the computation method of mmc clock divisor. 3)Updated exynos_dwmmc_init() to compute the 'clksel_val' within the function. Changes since V5: 1)Updated in response to review comments and changed the mmc clock value from 50MHz to 52MHz. Changes since V6: No change. Changes since V7: No change. arch/arm/include/asm/arch-exynos/dwmmc.h | 11 +-- drivers/mmc/exynos_dw_mmc.c | 127 ++++++++++++++++++++++++++++--- include/dwmmc.h | 3 + 3 files changed, 124 insertions(+), 17 deletions(-) diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h index 8acdf9b..3b147b8 100644 --- a/arch/arm/include/asm/arch-exynos/dwmmc.h +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h @@ -27,10 +27,7 @@ #define DWMCI_SET_DRV_CLK(x) ((x) << 16) #define DWMCI_SET_DIV_RATIO(x) ((x) << 24) -int exynos_dwmci_init(u32 regbase, int bus_width, int index); - -static inline unsigned int exynos_dwmmc_init(int index, int bus_width) -{ - unsigned int base = samsung_get_base_mmc() + (0x10000 * index); - return exynos_dwmci_init(base, bus_width, index); -} +#ifdef CONFIG_OF_CONTROL +int exynos_dwmmc_init(const void *blob); +#endif +int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel); diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index 72a31b7..4238dd9 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -19,39 +19,146 @@ */ #include -#include #include +#include +#include +#include #include #include +#include -static char *EXYNOS_NAME = "EXYNOS DWMMC"; +#define DWMMC_MAX_CH_NUM 4 +#define DWMMC_MAX_FREQ 52000000 +#define DWMMC_MIN_FREQ 400000 +#define DWMMC_MMC0_CLKSEL_VAL 0x03030001 +#define DWMMC_MMC2_CLKSEL_VAL 0x03020001 +/* + * Function used as callback function to initialise the + * CLKSEL register for every mmc channel. + */ static void exynos_dwmci_clksel(struct dwmci_host *host) { - u32 val; - val = DWMCI_SET_SAMPLE_CLK(DWMCI_SHIFT_0) | - DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) | DWMCI_SET_DIV_RATIO(0); + dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val); +} - dwmci_writel(host, DWMCI_CLKSEL, val); +unsigned int exynos_dwmci_get_clk(int dev_index) +{ + return get_mmc_clk(dev_index); } -int exynos_dwmci_init(u32 regbase, int bus_width, int index) +/* + * This function adds the mmc channel to be registered with mmc core. + * index - mmc channel number. + * regbase - register base address of mmc channel specified in 'index'. + * bus_width - operating bus width of mmc channel specified in 'index'. + * clksel - value to be written into CLKSEL register in case of FDT. + * NULL in case od non-FDT. + */ +int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel) { struct dwmci_host *host = NULL; + unsigned int div; + unsigned long freq, sclk; host = malloc(sizeof(struct dwmci_host)); if (!host) { printf("dwmci_host malloc fail!\n"); return 1; } + /* request mmc clock vlaue of 52MHz. */ + freq = 52000000; + sclk = get_mmc_clk(index); + div = DIV_ROUND_UP(sclk, freq); + /* set the clock divisor for mmc */ + set_mmc_clk(index, div); - host->name = EXYNOS_NAME; + host->name = "EXYNOS DWMMC"; host->ioaddr = (void *)regbase; host->buswidth = bus_width; + + if (clksel) { + host->clksel_val = clksel; + } else { + if (0 == index) + host->clksel_val = DWMMC_MMC0_CLKSEL_VAL; + if (2 == index) + host->clksel_val = DWMMC_MMC2_CLKSEL_VAL; + } + host->clksel = exynos_dwmci_clksel; host->dev_index = index; + host->mmc_clk = exynos_dwmci_get_clk; + /* Add the mmc channel to be registered with mmc core */ + if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) { + debug("dwmmc%d registration failed\n", index); + return -1; + } + return 0; +} + +#ifdef CONFIG_OF_CONTROL +int exynos_dwmmc_init(const void *blob) +{ + int index, bus_width; + int node_list[DWMMC_MAX_CH_NUM]; + int err = 0, dev_id, flag, count, i; + u32 clksel_val, base, timing[3]; + + count = fdtdec_find_aliases_for_id(blob, "mmc", + COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list, + DWMMC_MAX_CH_NUM); + + for (i = 0; i < count; i++) { + int node = node_list[i]; + + if (node <= 0) + continue; - add_dwmci(host, 52000000, 400000); + /* Extract device id for each mmc channel */ + dev_id = pinmux_decode_periph_id(blob, node); + /* Get the bus width from the device node */ + bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0); + if (bus_width <= 0) { + debug("DWMMC: Can't get bus-width\n"); + return -1; + } + if (8 == bus_width) + flag = PINMUX_FLAG_8BIT_MODE; + else + flag = PINMUX_FLAG_NONE; + + /* config pinmux for each mmc channel */ + err = exynos_pinmux_config(dev_id, flag); + if (err) { + debug("DWMMC not configured\n"); + return err; + } + + index = dev_id - PERIPH_ID_SDMMC0; + + /* Get the base address from the device node */ + base = fdtdec_get_addr(blob, node, "reg"); + if (!base) { + debug("DWMMC: Can't get base address\n"); + return -1; + } + /* Extract the timing info from the node */ + err = fdtdec_get_int_array(blob, node, "samsung,timing", + timing, 3); + if (err) { + debug("Can't get sdr-timings for divider\n"); + return -1; + } + + clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) | + DWMCI_SET_DRV_CLK(timing[1]) | + DWMCI_SET_DIV_RATIO(timing[2])); + /* Initialise each mmc channel */ + err = exynos_dwmci_add_port(index, base, bus_width, clksel_val); + if (err) + debug("dwmmc Channel-%d init failed\n", index); + } return 0; } - +#endif diff --git a/include/dwmmc.h b/include/dwmmc.h index c8b1d40..e142f3e 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -123,6 +123,8 @@ #define MSIZE(x) ((x) << 28) #define RX_WMARK(x) ((x) << 16) #define TX_WMARK(x) (x) +#define RX_WMARK_SHIFT 16 +#define RX_WMARK_MASK (0xfff << RX_WMARK_SHIFT) #define DWMCI_IDMAC_OWN (1 << 31) #define DWMCI_IDMAC_CH (1 << 4) @@ -144,6 +146,7 @@ struct dwmci_host { unsigned int bus_hz; int dev_index; int buswidth; + u32 clksel_val; u32 fifoth_val; struct mmc *mmc;