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[203.254.224.24]) by mx.google.com with ESMTP id xn6si26520889pbc.32.1969.12.31.16.00.00; Tue, 08 Oct 2013 06:11:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.24 as permitted sender) client-ip=203.254.224.24; Received: from epcpsbgr4.samsung.com (u144.gpu120.samsung.co.kr [203.254.230.144]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MUC0052OPY3AVN0@mailout1.samsung.com>; Tue, 08 Oct 2013 22:10:52 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.126]) by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id 20.5D.31253.B5404525; Tue, 08 Oct 2013 22:10:51 +0900 (KST) X-AuditID: cbfee690-b7f3b6d000007a15-68-5254045bf228 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 61.B1.05832.B5404525; Tue, 08 Oct 2013 22:10:51 +0900 (KST) Received: from localhost.localdomain.com ([107.108.73.95]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MUC002OQPXZX300@mmp2.samsung.com>; Tue, 08 Oct 2013 22:10:51 +0900 (KST) From: Rajeshwari S Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org, u-boot-review@google.com, jagannadh.teki@gmail.com, alim.akhtar@samsung.com Subject: [PATCH V3] exynos: spl: Add a custom spi copy function Date: Tue, 08 Oct 2013 18:42:22 +0530 Message-id: <1381237942-30354-1-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.11.7 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrBLMWRmVeSWpSXmKPExsWyRsSkTjeaJSTI4P0US4sH87axWTxcf5PF YtfWFlaLjiMtjBZTDn9hsfi2ZRujxfLXG9kt3u7tZHfg8JjdcJHFY+esu+weCzaVety5tofN 4+ydHYwefVtWMQawRXHZpKTmZJalFunbJXBlrJndwljQbVXx//47xgbGx/pdjJwcEgImEhf2 vWKFsMUkLtxbz9bFyMUhJLCUUeLm1sfMMEWzX8xjhUhMZ5SYf7KVBcLpYpK41nqXvYuRg4MN qGrjiQSQBhEBCYlf/VcZQWxmgdWMElMaqkBsYQF7ibYPH5hAbBYBVYnZuyaDLeAV8JA4vv0W O8QyRYkZS54xgsyXEJjMLtG/8wkrRIOAxLfJh1hAdkkIyEpsOgB1nKTEwRU3WCYwCi5gZFjF KJpakFxQnJReZKJXnJhbXJqXrpecn7uJERjKp/89m7CD8d4B60OMyUDjJjJLiSbnA2MhryTe 0NjMyMLUxNTYyNzSjDRhJXFe9RbrQCGB9MSS1OzU1ILUovii0pzU4kOMTBycUg2Mhh2bS0/d V1hukVEe+ClnvkTRhKjvW6InNns91ylbcmb9Zcl/PwK1StbPdgx7YfGlUU1SXyKiW+ZU6T8/ GwVxrkqGUEun+XN3C06I+Set6Zz5U2iyqr/2w5wj9S80I4s0Zj8X54leG7cmb0Efy8vbv13v LGZ87HDu/dGzh9+U+Hz/IHyf7/UeJZbijERDLeai4kQAgyAMyHsCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrKIsWRmVeSWpSXmKPExsVy+t9jQd1olpAgg1/b9SwezNvGZvFw/U0W i11bW1gtOo60MFpMOfyFxeLblm2MFstfb2S3eLu3k92Bw2N2w0UWj52z7rJ7LNhU6nHn2h42 j7N3djB69G1ZxRjAFtXAaJORmpiSWqSQmpecn5KZl26r5B0c7xxvamZgqGtoaWGupJCXmJtq q+TiE6DrlpkDdJGSQlliTilQKCCxuFhJ3w7ThNAQN10LmMYIXd+QILgeIwM0kLCGMWPN7BbG gm6riv/33zE2MD7W72Lk5JAQMJGY/WIeK4QtJnHh3nq2LkYuDiGB6YwS80+2skA4XUwS11rv sncxcnCwAXVsPJEA0iAiICHxq/8qI4jNLLCaUWJKQxWILSxgL9H24QMTiM0ioCoxe9dkZhCb V8BD4vj2W+wQyxQlZix5xjiBkXsBI8MqRtHUguSC4qT0XCO94sTc4tK8dL3k/NxNjOBIeSa9 g3FVg8UhRgEORiUeXoHDQUFCrIllxZW5hxglOJiVRHj5/gcHCfGmJFZWpRblxxeV5qQWH2JM Bto+kVlKNDkfGMV5JfGGxibmpsamliYWJmaWpAkrifMebLUOFBJITyxJzU5NLUgtgtnCxMEp 1cDoffRP8mZP7+Tnyd9VJpinz3del3KxNFWz6fmGmaaSZx4q5HBP0GYxcVDibOtLeX45w3nN 5vsS7E4mS6cE/390LXbH1e9F1zkdGr8oXGtwPz7P3/PyMa9Y452tt72adP4qKOfpNdZ3NQS8 W86Slv0yuvzELb1/MwX//WvZuDhMvJVh8syTdreVWIozEg21mIuKEwEjAByk2AIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: rajeshwari.s@samsung.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.170 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This patch implements a custom spi_copy funtion to copy u-boot from SF to RAM. This is faster then iROM spi_copy funtion as this runs spi at 50Mhz and also in WORD mode of operation. Changed a printf in pinmux.c to debug just to avoid the compilation error in SPL. Signed-off-by: Alim Akhtar Signed-off-by: Tom Wai-Hong Tam Signed-off-by: Rajeshwari S Shinde --- Based on following patch yet to be merged: "[U-Boot] [PATCH 4/4] spi: exynos: Support word transfers" Changes in V2: - Corrected the commit message. - Added a SPI timeout check. - Corrected the comments. Changes in V3: - Rebased on the latest u-boot-spi tree. arch/arm/cpu/armv7/exynos/pinmux.c | 2 +- arch/arm/cpu/armv7/exynos/spl_boot.c | 122 ++++++++++++++++++++++++++++++++- arch/arm/include/asm/arch-exynos/spi.h | 1 + include/configs/exynos5250-dt.h | 2 + 4 files changed, 123 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 8002bce..74cc700 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -462,7 +462,7 @@ static int exynos4_pinmux_config(int peripheral, int flags) case PERIPH_ID_SDMMC1: case PERIPH_ID_SDMMC3: case PERIPH_ID_SDMMC4: - printf("SDMMC device %d not implemented\n", peripheral); + debug("SDMMC device %d not implemented\n", peripheral); return -1; default: debug("%s: invalid peripheral %d", __func__, peripheral); diff --git a/arch/arm/cpu/armv7/exynos/spl_boot.c b/arch/arm/cpu/armv7/exynos/spl_boot.c index 3651c00..6faf13f 100644 --- a/arch/arm/cpu/armv7/exynos/spl_boot.c +++ b/arch/arm/cpu/armv7/exynos/spl_boot.c @@ -10,8 +10,11 @@ #include #include #include +#include +#include #include #include +#include #include "common_setup.h" #include "clock_init.h" @@ -59,6 +62,119 @@ static int config_branch_prediction(int set_cr_z) } #endif +static void spi_rx_tx(struct exynos_spi *regs, int todo, + void *dinp, void const *doutp, int i) +{ + uint *rxp = (uint *)(dinp + (i * (32 * 1024))); + int rx_lvl, tx_lvl; + uint out_bytes, in_bytes; + + out_bytes = todo; + in_bytes = todo; + setbits_le32(®s->ch_cfg, SPI_CH_RST); + clrbits_le32(®s->ch_cfg, SPI_CH_RST); + writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, ®s->pkt_cnt); + + while (in_bytes) { + uint32_t spi_sts; + int temp; + + spi_sts = readl(®s->spi_sts); + rx_lvl = ((spi_sts >> 15) & 0x7f); + tx_lvl = ((spi_sts >> 6) & 0x7f); + while (tx_lvl < 32 && out_bytes) { + temp = 0xffffffff; + writel(temp, ®s->tx_data); + out_bytes -= 4; + tx_lvl += 4; + } + while (rx_lvl >= 4 && in_bytes) { + temp = readl(®s->rx_data); + if (rxp) + *rxp++ = temp; + in_bytes -= 4; + rx_lvl -= 4; + } + } +} + +/* + * Copy uboot from spi flash to RAM + * + * @parma uboot_size size of u-boot to copy + * @param uboot_addr address in u-boot to copy + */ +static void exynos_spi_copy(unsigned int uboot_size, unsigned int uboot_addr) +{ + int upto, todo; + int i, timeout = 100; + struct exynos_spi *regs = (struct exynos_spi *)CONFIG_ENV_SPI_BASE; + + set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */ + /* set the spi1 GPIO */ + exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE); + + /* set pktcnt and enable it */ + writel(4 | SPI_PACKET_CNT_EN, ®s->pkt_cnt); + /* set FB_CLK_SEL */ + writel(SPI_FB_DELAY_180, ®s->fb_clk); + /* set CH_WIDTH and BUS_WIDTH as word */ + setbits_le32(®s->mode_cfg, SPI_MODE_CH_WIDTH_WORD | + SPI_MODE_BUS_WIDTH_WORD); + clrbits_le32(®s->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */ + + /* clear rx and tx channel if set priveously */ + clrbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); + + setbits_le32(®s->swap_cfg, SPI_RX_SWAP_EN | + SPI_RX_BYTE_SWAP | + SPI_RX_HWORD_SWAP); + + /* do a soft reset */ + setbits_le32(®s->ch_cfg, SPI_CH_RST); + clrbits_le32(®s->ch_cfg, SPI_CH_RST); + + /* now set rx and tx channel ON */ + setbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN); + clrbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */ + + /* Send read instruction (0x3h) followed by a 24 bit addr */ + writel((SF_READ_DATA_CMD << 24) | SPI_FLASH_UBOOT_POS, ®s->tx_data); + + /* waiting for TX done */ + while (!(readl(®s->spi_sts) & SPI_ST_TX_DONE)) { + if (!timeout) { + debug("SPI TIMEOUT\n"); + break; + } + timeout--; + } + + for (upto = 0, i = 0; upto < uboot_size; upto += todo, i++) { + todo = min(uboot_size - upto, (1 << 15)); + spi_rx_tx(regs, todo, (void *)(uboot_addr), + (void *)(SPI_FLASH_UBOOT_POS), i); + } + + setbits_le32(®s->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */ + + /* + * Let put controller mode to BYTE as + * SPI driver does not support WORD mode yet + */ + clrbits_le32(®s->mode_cfg, SPI_MODE_CH_WIDTH_WORD | + SPI_MODE_BUS_WIDTH_WORD); + writel(0, ®s->swap_cfg); + + /* + * Flush spi tx, rx fifos and reset the SPI controller + * and clear rx/tx channel + */ + clrsetbits_le32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST); + clrbits_le32(®s->ch_cfg, SPI_CH_RST); + clrbits_le32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON); +} + /* * Copy U-boot from mmc to RAM: * COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains @@ -70,6 +186,7 @@ void copy_uboot_to_ram(void) u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst) = NULL; u32 offset = 0, size = 0; + struct spl_machine_param *param = spl_get_machine_params(); #ifdef CONFIG_SUPPORT_EMMC_BOOT u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst); void (*end_bootop_from_emmc)(void); @@ -91,9 +208,8 @@ void copy_uboot_to_ram(void) switch (bootmode) { #ifdef CONFIG_SPI_BOOTING case BOOT_MODE_SERIAL: - offset = SPI_FLASH_UBOOT_POS; - size = CONFIG_BL2_SIZE; - copy_bl2 = get_irom_func(SPI_INDEX); + /* Customised function to copy u-boot from SF */ + exynos_spi_copy(param->uboot_size, CONFIG_SYS_TEXT_BASE); break; #endif case BOOT_MODE_MMC: diff --git a/arch/arm/include/asm/arch-exynos/spi.h b/arch/arm/include/asm/arch-exynos/spi.h index 147c1a7..0ba931b 100644 --- a/arch/arm/include/asm/arch-exynos/spi.h +++ b/arch/arm/include/asm/arch-exynos/spi.h @@ -30,6 +30,7 @@ struct exynos_spi { #define EXYNOS_SPI_MAX_FREQ 50000000 #define SPI_TIMEOUT_MS 10 +#define SF_READ_DATA_CMD 0x3 /* SPI_CHCFG */ #define SPI_CH_HS_EN (1 << 6) diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index 8c21909..1d32396 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -154,6 +154,7 @@ #define COPY_BL2_FNPTR_ADDR 0x02020030 #define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT /* specific .lds file */ #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" @@ -292,6 +293,7 @@ /* SPI */ #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_SPI_FLASH +#define CONFIG_ENV_SPI_BASE 0x12D30000 #ifdef CONFIG_SPI_FLASH #define CONFIG_EXYNOS_SPI