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[85.214.87.163]) by mx.google.com with ESMTP id d5si5676697wjb.130.2014.06.23.15.18.46 for ; Mon, 23 Jun 2014 15:18:46 -0700 (PDT) Received-SPF: none (google.com: u-boot-bounces@lists.denx.de does not designate permitted sender hosts) client-ip=85.214.87.163; Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1C129A74BC; Tue, 24 Jun 2014 00:18:46 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id u8m-O8b6dHEc; Tue, 24 Jun 2014 00:18:45 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6CBC6A74BD; Tue, 24 Jun 2014 00:18:42 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 84A25A74BD for ; Tue, 24 Jun 2014 00:18:38 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id R7C0lLMQqK+z for ; Tue, 24 Jun 2014 00:18:35 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40]) by theia.denx.de (Postfix) with ESMTPS id 467D3A74BC for ; Tue, 24 Jun 2014 00:18:30 +0200 (CEST) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id s5NMISxI012279; Mon, 23 Jun 2014 17:18:28 -0500 Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s5NMIR8p004304; Mon, 23 Jun 2014 17:18:28 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.174.1; Mon, 23 Jun 2014 17:18:27 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s5NMIQfX022234; Mon, 23 Jun 2014 17:18:27 -0500 From: Felipe Balbi To: Tom Rini Date: Mon, 23 Jun 2014 17:18:24 -0500 Message-ID: <1403561904-28935-1-git-send-email-balbi@ti.com> X-Mailer: git-send-email 2.0.0.390.gcb682f8 In-Reply-To: References: MIME-Version: 1.0 Cc: Steven Kipisz , u-boot@lists.denx.de, "Franklin Cooper Jr." Subject: [U-Boot] [PATCH v2 2/2] usb: phy: omap_usb_phy: implement usb_phy_power() for AM437x X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: balbi@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.175 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Newer AM437x silicon requires us to explicitly power up the USB2 PHY. By implementing usb_phy_power() we can achieve that. Signed-off-by: Felipe Balbi --- Changes since v1: - add macros for USB1_CTRL register and bits arch/arm/include/asm/arch-am33xx/hardware_am43xx.h | 5 +++++ drivers/usb/phy/omap_usb_phy.c | 17 ++++++++++++++++- 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h index 15399dc..b5875e3 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h @@ -40,6 +40,11 @@ #define VTP0_CTRL_ADDR 0x44E10E0C #define VTP1_CTRL_ADDR 0x48140E10 +/* USB CTRL Base Address */ +#define USB1_CTRL 0x44e10628 +#define USB1_CTRL_CM_PWRDN BIT(0) +#define USB1_CTRL_OTG_PWRDN BIT(1) + /* DDR Base address */ #define DDR_PHY_CMD_ADDR 0x44E12000 #define DDR_PHY_DATA_ADDR 0x44E120C8 diff --git a/drivers/usb/phy/omap_usb_phy.c b/drivers/usb/phy/omap_usb_phy.c index af46db2..f78d532 100644 --- a/drivers/usb/phy/omap_usb_phy.c +++ b/drivers/usb/phy/omap_usb_phy.c @@ -222,7 +222,22 @@ static void am437x_enable_usb2_phy2(struct omap_xhci *omap) void usb_phy_power(int on) { - return; + u32 val; + + /* USB1_CTRL */ + val = readl(USB1_CTRL); + if (on) { + /* + * these bits are re-used on AM437x to power up/down the USB + * CM and OTG PHYs, if we don't toggle them, USB will not be + * functional on newer silicon revisions + */ + val &= ~(USB1_CTRL_CM_PWRDN | USB1_CTRL_OTG_PWRDN); + } else { + val |= USB1_CTRL_CM_PWRDN | USB1_CTRL_OTG_PWRDN; + } + + writel(val, USB1_CTRL); } #endif /* CONFIG_AM437X_USB2PHY2_HOST */