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[85.214.87.163]) by mx.google.com with ESMTP id ck2si2037277wjc.147.2015.01.27.04.46.28; Tue, 27 Jan 2015 04:46:29 -0800 (PST) Received-SPF: none (google.com: u-boot-bounces@lists.denx.de does not designate permitted sender hosts) client-ip=85.214.87.163; Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C74724B61A; Tue, 27 Jan 2015 13:46:28 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id nqW7p7-BRIZJ; Tue, 27 Jan 2015 13:46:28 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5B5A84B5FA; Tue, 27 Jan 2015 13:46:28 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 715804B5FA for ; Tue, 27 Jan 2015 13:46:23 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id zDXQUUH1SzSn for ; Tue, 27 Jan 2015 13:46:23 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-la0-f48.google.com (mail-la0-f48.google.com [209.85.215.48]) by theia.denx.de (Postfix) with ESMTPS id 3D0FF4B5F5 for ; Tue, 27 Jan 2015 13:46:20 +0100 (CET) Received: by mail-la0-f48.google.com with SMTP id pv20so12985417lab.7 for ; Tue, 27 Jan 2015 04:46:20 -0800 (PST) X-Received: by 10.152.1.2 with SMTP id 2mr1302607lai.89.1422362780051; Tue, 27 Jan 2015 04:46:20 -0800 (PST) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id e7sm414902lbq.33.2015.01.27.04.46.17 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 27 Jan 2015 04:46:18 -0800 (PST) From: Linus Walleij To: u-boot@lists.denx.de, Albert Aribaud , Tom Rini Date: Tue, 27 Jan 2015 13:46:11 +0100 Message-Id: <1422362771-26991-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.9.3 Cc: Steve Rae , David Feng , u-boot-review@google.com Subject: [U-Boot] [PATCH] armv8/vexpress64: make multientry conditional X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: linus.walleij@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.181 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 While the Freescale ARMv8 board LS2085A will enter U-Boot both on a master and a secondary (slave) CPU, this is not the common behaviour on ARMv8 platforms. The norm is that U-Boot is entered from the master CPU only, while the other CPUs are kept in WFI (wait for interrupt) state. The code determining which CPU we are running on is using the MPIDR register, but the definition of that register varies with platform to some extent, and handling multi-cluster platforms (such as the Juno) will become cumbersome. It is better to only enable the multiple entry code on machines that actually need it and disable it by default. Make the single entry default and add a special CONFIG_ARMV8_MULTIENTRY config option to be used by the platforms that need multientry and set it for the LS2085A. Delete all use of the CPU_RELEASE_ADDR from the Vexpress64 boards as it is just totally unused and misleading, and make it conditional in the generic start.S code. This makes the Juno platform start U-Boot properly. Signed-off-by: Linus Walleij --- This patch applied on top of the other patch series send, ending with [PATCH 4/4] vexpress64: support the Juno Development Platform Please apply it on top of these if the patch seems OK. --- arch/arm/cpu/armv8/start.S | 8 ++++---- arch/arm/include/asm/macro.h | 8 ++++++++ board/armltd/vexpress64/vexpress64.c | 6 ------ include/configs/ls2085a_common.h | 5 +++++ include/configs/vexpress_aemv8a.h | 8 -------- 5 files changed, 17 insertions(+), 18 deletions(-) diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index 4b11aa4f2227..9b439f30b779 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -77,6 +77,7 @@ reset: /* Processor specific initialization */ bl lowlevel_init +#ifdef CONFIG_ARMV8_MULTIENTRY branch_if_master x0, x1, master_cpu /* @@ -88,11 +89,10 @@ slave_cpu: ldr x0, [x1] cbz x0, slave_cpu br x0 /* branch to the given address */ - - /* - * Master CPU - */ master_cpu: + /* On the master CPU */ +#endif /* CONFIG_ARMV8_MULTIENTRY */ + bl _main /*-----------------------------------------------------------------------*/ diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h index 1c8c4251ee0c..3b3146ab2239 100644 --- a/arch/arm/include/asm/macro.h +++ b/arch/arm/include/asm/macro.h @@ -78,6 +78,8 @@ lr .req x30 * choose processor with all zero affinity value as the master. */ .macro branch_if_slave, xreg, slave_label +#ifdef CONFIG_ARMV8_MULTIENTRY + /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */ mrs \xreg, mpidr_el1 tst \xreg, #0xff /* Test Affinity 0 */ b.ne \slave_label @@ -90,6 +92,7 @@ lr .req x30 lsr \xreg, \xreg, #16 tst \xreg, #0xff /* Test Affinity 3 */ b.ne \slave_label +#endif .endm /* @@ -97,12 +100,17 @@ lr .req x30 * choose processor with all zero affinity value as the master. */ .macro branch_if_master, xreg1, xreg2, master_label +#ifdef CONFIG_ARMV8_MULTIENTRY + /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */ mrs \xreg1, mpidr_el1 lsr \xreg2, \xreg1, #32 lsl \xreg1, \xreg1, #40 lsr \xreg1, \xreg1, #40 orr \xreg1, \xreg1, \xreg2 cbz \xreg1, \master_label +#else + b \master_label +#endif .endm .macro armv8_switch_to_el2_m, xreg1 diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index 58973185ecda..7ab000cca77b 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -22,12 +22,6 @@ int board_init(void) int dram_init(void) { - /* - * Clear spin table so that secondary processors - * observe the correct value after waken up from wfe. - */ - *(unsigned long *)CPU_RELEASE_ADDR = 0; - gd->ram_size = PHYS_SDRAM_1_SIZE; return 0; } diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index 6fe032c9ff64..7f6f6f34cfa4 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -8,6 +8,11 @@ #define __LS2_COMMON_H #define CONFIG_SYS_GENERIC_BOARD +/* + * These machines will enter U-Boot on the master CPU and also + * a secondary CPU, so we need to handle that. + */ +#define CONFIG_ARMV8_MULTIENTRY #define CONFIG_REMAKE_ELF #define CONFIG_FSL_LSCH3 diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index 7fb28a54ba17..e276fff7e442 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -56,14 +56,6 @@ /* Flat Device Tree Definitions */ #define CONFIG_OF_LIBFDT - -/* SMP Spin Table Definitions */ -#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP -#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) -#else -#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) -#endif - /* CS register bases for the original memory map. */ #define V2M_PA_CS0 0x00000000 #define V2M_PA_CS1 0x14000000