From patchwork Fri Feb 26 05:21:46 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 62938 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp529127lbc; Thu, 25 Feb 2016 21:24:40 -0800 (PST) X-Received: by 10.28.153.19 with SMTP id b19mr1112151wme.14.1456464280104; Thu, 25 Feb 2016 21:24:40 -0800 (PST) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id e86si2076891wmc.31.2016.02.25.21.24.39; Thu, 25 Feb 2016 21:24:40 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3EBDAA7838; Fri, 26 Feb 2016 06:23:12 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 74i6JSeLCSKe; Fri, 26 Feb 2016 06:23:12 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 840C6A77E3; Fri, 26 Feb 2016 06:22:17 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E237CA7766 for ; Fri, 26 Feb 2016 06:21:29 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id a_W2LzIilD89 for ; Fri, 26 Feb 2016 06:21:29 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from conuserg009-v.nifty.com (conuserg009.nifty.com [202.248.44.35]) by theia.denx.de (Postfix) with ESMTPS id 3AE24A776C for ; Fri, 26 Feb 2016 06:21:24 +0100 (CET) Received: from beagle.diag.org (p14090-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.90]) (authenticated) by conuserg009-v.nifty.com with ESMTP id u1Q5L8l9000668; Fri, 26 Feb 2016 14:21:17 +0900 X-Nifty-SrcIP: [153.142.97.90] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Fri, 26 Feb 2016 14:21:46 +0900 Message-Id: <1456464113-13901-15-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1456464113-13901-1-git-send-email-yamada.masahiro@socionext.com> References: <1456464113-13901-1-git-send-email-yamada.masahiro@socionext.com> Subject: [U-Boot] [PATCH 14/21] ARM: uniphier: refactor UMC init code for PH1-LD4 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Move frequency-dependent register settings to arrays for clean-up. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/dram/umc-ph1-ld4.c | 79 +++++++++++++++++++++---------- 1 file changed, 55 insertions(+), 24 deletions(-) -- 1.9.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c index bee3ef4..353ef69 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c @@ -13,6 +13,27 @@ #include "ddrphy-regs.h" #include "umc-regs.h" +enum dram_freq { + DRAM_FREQ_1333M, + DRAM_FREQ_1600M, + DRAM_FREQ_NR, +}; + +enum dram_size { + DRAM_SZ_128M, + DRAM_SZ_256M, + DRAM_SZ_NR, +}; + +static u32 umc_cmdctla_plus[DRAM_FREQ_NR] = {0x45990b11, 0x36bb0f17}; +static u32 umc_cmdctlb_plus[DRAM_FREQ_NR] = {0x16958924, 0x18c6aa24}; +static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = { + {0x00240512, 0x00350512}, + {0x002b0617, 0x003f0617}, +}; +static u32 umc_spcctlb[DRAM_FREQ_NR] = {0x00ff0006, 0x00ff0008}; +static u32 umc_rdatactl[DRAM_FREQ_NR] = {0x000a00ac, 0x000c00ae}; + static void umc_start_ssif(void __iomem *ssif_base) { writel(0x00000000, ssif_base + 0x0000b004); @@ -47,35 +68,43 @@ static void umc_start_ssif(void __iomem *ssif_base) writel(0x00000001, ssif_base + UMC_DMDRST); } -static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, - int size, int freq) +static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, + int size, int freq) { - if (freq == 1333) { - writel(0x45990b11, dramcont + UMC_CMDCTLA); - writel(0x16958924, dramcont + UMC_CMDCTLB); - } else if (freq == 1600) { - writel(0x36BB0F17, dramcont + UMC_CMDCTLA); - writel(0x18C6AA24, dramcont + UMC_CMDCTLB); + enum dram_freq freq_e; + enum dram_size size_e; + + switch (freq) { + case 1333: + freq_e = DRAM_FREQ_1333M; + break; + case 1600: + freq_e = DRAM_FREQ_1600M; + break; + default: + pr_err("unsupported DRAM frequency %d MHz\n", freq); + return -EINVAL; } - if (freq == 1333) { - if (size == 1) - writel(0x00240512, dramcont + UMC_SPCCTLA); - else if (size == 2) - writel(0x00350512, dramcont + UMC_SPCCTLA); - - writel(0x00ff0006, dramcont + UMC_SPCCTLB); - writel(0x000a00ac, dramcont + UMC_RDATACTL_D0); - } else if (freq == 1600) { - if (size == 1) - writel(0x002B0617, dramcont + UMC_SPCCTLA); - else if (size == 2) - writel(0x003F0617, dramcont + UMC_SPCCTLA); - - writel(0x00ff0008, dramcont + UMC_SPCCTLB); - writel(0x000c00ae, dramcont + UMC_RDATACTL_D0); + switch (size) { + case 0: + return 0; + case 1: + size_e = DRAM_SZ_128M; + break; + case 2: + size_e = DRAM_SZ_256M; + break; + default: + pr_err("unsupported DRAM size\n"); + return -EINVAL; } + writel(umc_cmdctla_plus[freq_e], dramcont + UMC_CMDCTLA); + writel(umc_cmdctlb_plus[freq_e], dramcont + UMC_CMDCTLB); + writel(umc_spcctla[freq_e][size_e], dramcont + UMC_SPCCTLA); + writel(umc_spcctlb[freq_e], dramcont + UMC_SPCCTLB); + writel(umc_rdatactl[freq_e], dramcont + UMC_RDATACTL_D0); writel(0x04060806, dramcont + UMC_WDATACTL_D0); writel(0x04a02000, dramcont + UMC_DATASET); writel(0x00000000, ca_base + 0x2300); @@ -94,6 +123,8 @@ static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, writel(0x200a0a00, dramcont + UMC_SPCSETB); writel(0x00000000, dramcont + UMC_SPCSETD); writel(0x00000520, dramcont + UMC_DFICUPDCTLA); + + return 0; } static int umc_init_sub(int freq, int size_ch0, int size_ch1, bool ddr3plus)