From patchwork Fri Feb 26 05:21:48 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 62926 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp528385lbc; Thu, 25 Feb 2016 21:21:56 -0800 (PST) X-Received: by 10.194.58.12 with SMTP id m12mr54091012wjq.22.1456464116763; Thu, 25 Feb 2016 21:21:56 -0800 (PST) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id pi3si13877338wjb.134.2016.02.25.21.21.56; Thu, 25 Feb 2016 21:21:56 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AECE2A767F; Fri, 26 Feb 2016 06:21:52 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id v8-gzL2s_ecb; Fri, 26 Feb 2016 06:21:52 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8551CA7767; Fri, 26 Feb 2016 06:21:51 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 31AF0A7767 for ; Fri, 26 Feb 2016 06:21:28 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id j_uDM6n-5k4d for ; Fri, 26 Feb 2016 06:21:28 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from conuserg009-v.nifty.com (conuserg009.nifty.com [202.248.44.35]) by theia.denx.de (Postfix) with ESMTPS id 44F19A7747 for ; Fri, 26 Feb 2016 06:21:24 +0100 (CET) Received: from beagle.diag.org (p14090-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.90]) (authenticated) by conuserg009-v.nifty.com with ESMTP id u1Q5L8lB000668; Fri, 26 Feb 2016 14:21:18 +0900 X-Nifty-SrcIP: [153.142.97.90] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Fri, 26 Feb 2016 14:21:48 +0900 Message-Id: <1456464113-13901-17-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1456464113-13901-1-git-send-email-yamada.masahiro@socionext.com> References: <1456464113-13901-1-git-send-email-yamada.masahiro@socionext.com> Subject: [U-Boot] [PATCH 16/21] ARM: uniphier: optimize PH1-LD4 UMC init code with "for" loop X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Now this code can be re-written with a "for" statement instead of calling the same function multiple times. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/dram/umc-ph1-ld4.c | 90 +++++++++++++++++-------------- 1 file changed, 49 insertions(+), 41 deletions(-) -- 1.9.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c index 353ef69..92b0f18 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c @@ -13,6 +13,8 @@ #include "ddrphy-regs.h" #include "umc-regs.h" +#define DRAM_CH_NR 2 + enum dram_freq { DRAM_FREQ_1333M, DRAM_FREQ_1600M, @@ -34,6 +36,11 @@ static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = { static u32 umc_spcctlb[DRAM_FREQ_NR] = {0x00ff0006, 0x00ff0008}; static u32 umc_rdatactl[DRAM_FREQ_NR] = {0x000a00ac, 0x000c00ae}; +static int umc_get_rank(int ch) +{ + return ch; /* ch0: rank0, ch1: rank1 for this SoC */ +} + static void umc_start_ssif(void __iomem *ssif_base) { writel(0x00000000, ssif_base + 0x0000b004); @@ -69,11 +76,16 @@ static void umc_start_ssif(void __iomem *ssif_base) } static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, - int size, int freq) + int size, int freq, bool ddr3plus) { enum dram_freq freq_e; enum dram_size size_e; + if (!ddr3plus) { + pr_err("DDR3 standard is not supported\n"); + return -EINVAL; + } + switch (freq) { case 1333: freq_e = DRAM_FREQ_1333M; @@ -127,55 +139,51 @@ static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, return 0; } -static int umc_init_sub(int freq, int size_ch0, int size_ch1, bool ddr3plus) +static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base, + int freq, int size, bool ddr3plus, int ch) { - void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE; - void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0); - void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1); - void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0); - void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1); - void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0); - void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0); - - umc_dram_init_start(dramcont0); - umc_dram_init_start(dramcont1); - umc_dram_init_poll(dramcont0); - umc_dram_init_poll(dramcont1); - - writel(0x00000101, dramcont0 + UMC_DIOCTLA); - - ph1_ld4_ddrphy_init(phy0_0, freq, ddr3plus); + void __iomem *phy_base = dc_base + 0x00001000; + int ret; - ddrphy_prepare_training(phy0_0, 0); - ddrphy_training(phy0_0); + umc_dram_init_start(dc_base); + umc_dram_init_poll(dc_base); - writel(0x00000101, dramcont1 + UMC_DIOCTLA); + writel(0x00000101, dc_base + UMC_DIOCTLA); - ph1_ld4_ddrphy_init(phy1_0, freq, ddr3plus); + ret = ph1_ld4_ddrphy_init(phy_base, freq, ddr3plus); + if (ret) + return ret; - ddrphy_prepare_training(phy1_0, 1); - ddrphy_training(phy1_0); + ddrphy_prepare_training(phy_base, umc_get_rank(ch)); + ret = ddrphy_training(phy_base); + if (ret) + return ret; - umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq); - umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq); - - umc_start_ssif(ssif_base); - - return 0; + return umc_dramcont_init(dc_base, ca_base, size, freq, ddr3plus); } int ph1_ld4_umc_init(const struct uniphier_board_data *bd) { - if ((bd->dram_ch[0].size == SZ_128M || bd->dram_ch[0].size == SZ_256M) && - (bd->dram_ch[1].size == SZ_128M || bd->dram_ch[1].size == SZ_256M) && - (bd->dram_freq == 1333 || bd->dram_freq == 1600) && - bd->dram_ch[0].width == 16 && bd->dram_ch[1].width == 16) { - return umc_init_sub(bd->dram_freq, - bd->dram_ch[0].size / SZ_128M, - bd->dram_ch[1].size / SZ_128M, - bd->dram_ddr3plus); - } else { - pr_err("Unsupported DDR configuration\n"); - return -EINVAL; + void __iomem *umc_base = (void __iomem *)0x5b800000; + void __iomem *ca_base = umc_base + 0x00001000; + void __iomem *dc_base = umc_base + 0x00400000; + void __iomem *ssif_base = umc_base; + int ch, ret; + + for (ch = 0; ch < DRAM_CH_NR; ch++) { + ret = umc_ch_init(dc_base, ca_base, bd->dram_freq, + bd->dram_ch[ch].size / SZ_128M, + bd->dram_ddr3plus, ch); + if (ret) { + pr_err("failed to initialize UMC ch%d\n", ch); + return ret; + } + + ca_base += 0x00001000; + dc_base += 0x00200000; } + + umc_start_ssif(ssif_base); + + return 0; }