From patchwork Fri Feb 26 05:21:40 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 62929 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp528541lbc; Thu, 25 Feb 2016 21:22:31 -0800 (PST) X-Received: by 10.194.242.202 with SMTP id ws10mr30600763wjc.3.1456464151902; Thu, 25 Feb 2016 21:22:31 -0800 (PST) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id v131si2052609wme.78.2016.02.25.21.22.31; Thu, 25 Feb 2016 21:22:31 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5CCE3A77F9; Fri, 26 Feb 2016 06:22:10 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id SLqsUn7ISOf7; Fri, 26 Feb 2016 06:22:10 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 18D78A77D6; Fri, 26 Feb 2016 06:21:57 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7F64FA778B for ; Fri, 26 Feb 2016 06:21:28 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id TaXp3Bc8-APb for ; Fri, 26 Feb 2016 06:21:28 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from conuserg009-v.nifty.com (conuserg009.nifty.com [202.248.44.35]) by theia.denx.de (Postfix) with ESMTPS id 25E2AA74E0 for ; Fri, 26 Feb 2016 06:21:24 +0100 (CET) Received: from beagle.diag.org (p14090-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.90]) (authenticated) by conuserg009-v.nifty.com with ESMTP id u1Q5L8l3000668; Fri, 26 Feb 2016 14:21:13 +0900 X-Nifty-SrcIP: [153.142.97.90] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Fri, 26 Feb 2016 14:21:40 +0900 Message-Id: <1456464113-13901-9-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1456464113-13901-1-git-send-email-yamada.masahiro@socionext.com> References: <1456464113-13901-1-git-send-email-yamada.masahiro@socionext.com> Subject: [U-Boot] [PATCH 08/21] ARM: uniphier: add a field to specify DDR3+ X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add a field to distinguish DDR3+ from (standard) DDR3. It also allows to delete CONFIG_DDR_STANDARD (this is not a software configuration, but a board attribute). Default DDR3 spec for each SoC: PH1-LD4, PH1-sLD8: DDR3+ Others: DDR3 Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/boards.c | 2 ++ arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c | 5 +++-- arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c | 5 +++-- arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c | 9 +++------ arch/arm/mach-uniphier/dram/ddrphy-regs.h | 10 +++++++--- arch/arm/mach-uniphier/dram/umc-ph1-ld4.c | 9 +++++---- arch/arm/mach-uniphier/dram/umc-ph1-pro4.c | 12 ++++++++---- arch/arm/mach-uniphier/dram/umc-ph1-sld8.c | 24 ++++++++++-------------- arch/arm/mach-uniphier/init.h | 3 +++ 9 files changed, 44 insertions(+), 35 deletions(-) -- 1.9.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c index 05b7c76..408aff0 100644 --- a/arch/arm/mach-uniphier/boards.c +++ b/arch/arm/mach-uniphier/boards.c @@ -38,6 +38,7 @@ static const struct uniphier_board_data ph1_sld3_data = { static const struct uniphier_board_data ph1_ld4_data = { .dram_freq = 1600, .dram_nr_ch = 2, + .dram_ddr3plus = true, .dram_ch[0] = { .base = 0x80000000, .size = 0x10000000, @@ -89,6 +90,7 @@ static const struct uniphier_board_data ph1_pro4_2g_data = { static const struct uniphier_board_data ph1_sld8_data = { .dram_freq = 1333, .dram_nr_ch = 2, + .dram_ddr3plus = true, .dram_ch[0] = { .base = 0x80000000, .size = 0x10000000, diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c index d2bc5a1..3000a28 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c +++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c @@ -9,7 +9,8 @@ #include "ddrphy-regs.h" -int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) +int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size, + bool ddr3plus) { u32 tmp; @@ -61,7 +62,7 @@ int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) else writel(0x00000298, &phy->mr2); - writel(0x00000800, &phy->mr3); + writel(ddr3plus ? 0x00000800 : 0x00000000, &phy->mr3); while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE)) ; diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c index 9fb34f7..b4dca35 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c +++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-pro4.c @@ -9,7 +9,8 @@ #include "ddrphy-regs.h" -int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) +int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size, + bool ddr3plus) { u32 tmp; @@ -55,7 +56,7 @@ int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) else writel(0x00000298, &phy->mr2); - writel(0x00000000, &phy->mr3); + writel(ddr3plus ? 0x00000800 : 0x00000000, &phy->mr3); while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE)) ; diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c index 6510690..0d2ae42 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c +++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-sld8.c @@ -10,7 +10,8 @@ #include "ddrphy-regs.h" -int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) +int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size, + bool ddr3plus) { u32 tmp; @@ -62,11 +63,7 @@ int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) else writel(0x00000298, &phy->mr2); -#ifdef CONFIG_DDR_STANDARD - writel(0x00000000, &phy->mr3); -#else - writel(0x00000800, &phy->mr3); -#endif + writel(ddr3plus ? 0x00000800 : 0x00000000, &phy->mr3); while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE)) ; diff --git a/arch/arm/mach-uniphier/dram/ddrphy-regs.h b/arch/arm/mach-uniphier/dram/ddrphy-regs.h index 03aedc2..206fabd 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-regs.h +++ b/arch/arm/mach-uniphier/dram/ddrphy-regs.h @@ -11,6 +11,7 @@ #include #include +#include #ifndef __ASSEMBLY__ @@ -169,9 +170,12 @@ struct ddrphy { #define DDRPHY_BASE(ch, phy) (0x5bc01000 + 0x200000 * (ch) + 0x1000 * (phy)) #ifndef __ASSEMBLY__ -int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size); -int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size); -int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size); +int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size, + bool ddr3plus); +int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size, + bool ddr3plus); +int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size, + bool ddr3plus); void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank); int ddrphy_training(struct ddrphy __iomem *phy); #endif diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c index 638aa11..957a38f 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c @@ -96,7 +96,7 @@ static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, writel(0x00000520, dramcont + UMC_DFICUPDCTLA); } -static int umc_init_sub(int freq, int size_ch0, int size_ch1) +static int umc_init_sub(int freq, int size_ch0, int size_ch1, bool ddr3plus) { void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE; void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0); @@ -113,14 +113,14 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1) writel(0x00000101, dramcont0 + UMC_DIOCTLA); - ph1_ld4_ddrphy_init(phy0_0, freq, size_ch0); + ph1_ld4_ddrphy_init(phy0_0, freq, size_ch0, ddr3plus); ddrphy_prepare_training(phy0_0, 0); ddrphy_training(phy0_0); writel(0x00000101, dramcont1 + UMC_DIOCTLA); - ph1_ld4_ddrphy_init(phy1_0, freq, size_ch1); + ph1_ld4_ddrphy_init(phy1_0, freq, size_ch1, ddr3plus); ddrphy_prepare_training(phy1_0, 1); ddrphy_training(phy1_0); @@ -141,7 +141,8 @@ int ph1_ld4_umc_init(const struct uniphier_board_data *bd) bd->dram_ch[0].width == 16 && bd->dram_ch[1].width == 16) { return umc_init_sub(bd->dram_freq, bd->dram_ch[0].size / SZ_128M, - bd->dram_ch[1].size / SZ_128M); + bd->dram_ch[1].size / SZ_128M, + bd->dram_ddr3plus); } else { pr_err("Unsupported DDR configuration\n"); return -EINVAL; diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c index f89b1da..38dd338 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c @@ -138,28 +138,32 @@ int ph1_pro4_umc_init(const struct uniphier_board_data *bd) writel(0x00000101, dramcont0 + UMC_DIOCTLA); - ph1_pro4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ch[0].size); + ph1_pro4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ch[0].size, + bd->dram_ddr3plus); ddrphy_prepare_training(phy0_0, 0); ddrphy_training(phy0_0); writel(0x00000103, dramcont0 + UMC_DIOCTLA); - ph1_pro4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ch[0].size); + ph1_pro4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ch[0].size, + bd->dram_ddr3plus); ddrphy_prepare_training(phy0_1, 1); ddrphy_training(phy0_1); writel(0x00000101, dramcont1 + UMC_DIOCTLA); - ph1_pro4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ch[1].size); + ph1_pro4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ch[1].size, + bd->dram_ddr3plus); ddrphy_prepare_training(phy1_0, 0); ddrphy_training(phy1_0); writel(0x00000103, dramcont1 + UMC_DIOCTLA); - ph1_pro4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ch[1].size); + ph1_pro4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ch[1].size, + bd->dram_ddr3plus); ddrphy_prepare_training(phy1_1, 1); ddrphy_training(phy1_1); diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c index fa0619f..3cbb7ba 100644 --- a/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c +++ b/arch/arm/mach-uniphier/dram/umc-ph1-sld8.c @@ -48,15 +48,10 @@ static void umc_start_ssif(void __iomem *ssif_base) } static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, - int size, int freq) + int size, int freq, bool ddr3plus) { -#ifdef CONFIG_DDR_STANDARD - writel(0x55990b11, dramcont + UMC_CMDCTLA); - writel(0x16958944, dramcont + UMC_CMDCTLB); -#else - writel(0x45990b11, dramcont + UMC_CMDCTLA); - writel(0x16958924, dramcont + UMC_CMDCTLB); -#endif + writel(ddr3plus ? 0x45990b11 : 0x55990b11, dramcont + UMC_CMDCTLA); + writel(ddr3plus ? 0x16958924 : 0x16958944, dramcont + UMC_CMDCTLB); if (size == 1) writel(0x00240512, dramcont + UMC_SPCCTLA); @@ -85,7 +80,7 @@ static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, writel(0x00000520, dramcont + UMC_DFICUPDCTLA); } -static int umc_init_sub(int freq, int size_ch0, int size_ch1) +static int umc_init_sub(int freq, int size_ch0, int size_ch1, bool ddr3plus) { void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE; void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0); @@ -102,20 +97,20 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1) writel(0x00000101, dramcont0 + UMC_DIOCTLA); - ph1_sld8_ddrphy_init(phy0_0, freq, size_ch0); + ph1_sld8_ddrphy_init(phy0_0, freq, size_ch0, ddr3plus); ddrphy_prepare_training(phy0_0, 0); ddrphy_training(phy0_0); writel(0x00000101, dramcont1 + UMC_DIOCTLA); - ph1_sld8_ddrphy_init(phy1_0, freq, size_ch1); + ph1_sld8_ddrphy_init(phy1_0, freq, size_ch1, ddr3plus); ddrphy_prepare_training(phy1_0, 1); ddrphy_training(phy1_0); - umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq); - umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq); + umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq, ddr3plus); + umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq, ddr3plus); umc_start_ssif(ssif_base); @@ -130,7 +125,8 @@ int ph1_sld8_umc_init(const struct uniphier_board_data *bd) bd->dram_ch[0].width == 16 && bd->dram_ch[1].width == 16) { return umc_init_sub(bd->dram_freq, bd->dram_ch[0].size / SZ_128M, - bd->dram_ch[1].size / SZ_128M); + bd->dram_ch[1].size / SZ_128M, + bd->dram_ddr3plus); } else { pr_err("Unsupported DDR configuration\n"); return -EINVAL; diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h index aabd84a..e969fd0 100644 --- a/arch/arm/mach-uniphier/init.h +++ b/arch/arm/mach-uniphier/init.h @@ -7,6 +7,8 @@ #ifndef __MACH_INIT_H #define __MACH_INIT_H +#include + #define UNIPHIER_MAX_NR_DRAM_CH 3 struct uniphier_dram_ch { @@ -18,6 +20,7 @@ struct uniphier_dram_ch { struct uniphier_board_data { unsigned int dram_freq; unsigned int dram_nr_ch; + bool dram_ddr3plus; struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH]; };