From patchwork Tue Mar 15 15:25:53 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 63889 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp734586lbc; Tue, 15 Mar 2016 08:27:16 -0700 (PDT) X-Received: by 10.194.112.34 with SMTP id in2mr33602515wjb.160.1458055636889; Tue, 15 Mar 2016 08:27:16 -0700 (PDT) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id di9si33415696wjb.191.2016.03.15.08.27.16; Tue, 15 Mar 2016 08:27:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B1866A7701; Tue, 15 Mar 2016 16:27:09 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id q12HaLmSgBRp; Tue, 15 Mar 2016 16:27:09 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6A59EA76F6; Tue, 15 Mar 2016 16:27:00 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 46241A76B2 for ; Tue, 15 Mar 2016 16:26:52 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 7y74gAlxUxF3 for ; Tue, 15 Mar 2016 16:26:52 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40]) by theia.denx.de (Postfix) with ESMTPS id CCE51A76A3 for ; Tue, 15 Mar 2016 16:26:48 +0100 (CET) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id u2FFQkiq029243; Tue, 15 Mar 2016 10:26:46 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id u2FFQkTD025771; Tue, 15 Mar 2016 10:26:46 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.224.2; Tue, 15 Mar 2016 10:26:46 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id u2FFQjU1005201; Tue, 15 Mar 2016 10:26:46 -0500 From: Nishanth Menon To: Tom Rini Date: Tue, 15 Mar 2016 10:25:53 -0500 Message-ID: <1458055553-10818-4-git-send-email-nm@ti.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1458055553-10818-1-git-send-email-nm@ti.com> References: <1458055553-10818-1-git-send-email-nm@ti.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 3/3] ARM: keystone2: Convert BOOT_SET_BITFIELD into static inline function X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Fix up BOOT_SET_BITFIELD to be a static inline function to be readable with the same functionality. Reported-by: Tom Rini Signed-off-by: Nishanth Menon --- arch/arm/mach-keystone/include/mach/psc_defs.h | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) -- 2.7.0 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/arch/arm/mach-keystone/include/mach/psc_defs.h b/arch/arm/mach-keystone/include/mach/psc_defs.h index 671b1d64d69f..18499386a321 100644 --- a/arch/arm/mach-keystone/include/mach/psc_defs.h +++ b/arch/arm/mach-keystone/include/mach/psc_defs.h @@ -40,12 +40,16 @@ static inline u32 boot_read_bitfield(u32 z, u32 x, u32 y) return val >> y; } -#define BOOT_SET_BITFIELD(z, f, x, y) ((((u32)z) & ~_boot_bit_mask(x, y)) | \ - ((((u32)f) << (y)) & _boot_bit_mask(x, y))) +static inline u32 boot_set_bitfield(u32 z, u32 f, u32 x, u32 y) +{ + u32 mask = _boot_bit_mask(x, y); + + return (z & ~mask) | ((f << y) & mask); +} /* PDCTL */ -#define PSC_REG_PDCTL_SET_NEXT(x, y) BOOT_SET_BITFIELD((x), (y), 0, 0) -#define PSC_REG_PDCTL_SET_PDMODE(x, y) BOOT_SET_BITFIELD((x), (y), 15, 12) +#define PSC_REG_PDCTL_SET_NEXT(x, y) boot_set_bitfield((x), (y), 0, 0) +#define PSC_REG_PDCTL_SET_PDMODE(x, y) boot_set_bitfield((x), (y), 15, 12) /* PDSTAT */ #define PSC_REG_PDSTAT_GET_STATE(x) boot_read_bitfield((x), 4, 0) @@ -55,10 +59,10 @@ static inline u32 boot_read_bitfield(u32 z, u32 x, u32 y) #define PSC_REG_MDCFG_GET_RESET_ISO(x) boot_read_bitfield((x), 14, 14) /* MDCTL */ -#define PSC_REG_MDCTL_SET_NEXT(x, y) BOOT_SET_BITFIELD((x), (y), 4, 0) -#define PSC_REG_MDCTL_SET_LRSTZ(x, y) BOOT_SET_BITFIELD((x), (y), 8, 8) +#define PSC_REG_MDCTL_SET_NEXT(x, y) boot_set_bitfield((x), (y), 4, 0) +#define PSC_REG_MDCTL_SET_LRSTZ(x, y) boot_set_bitfield((x), (y), 8, 8) #define PSC_REG_MDCTL_GET_LRSTZ(x) boot_read_bitfield((x), 8, 8) -#define PSC_REG_MDCTL_SET_RESET_ISO(x, y) BOOT_SET_BITFIELD((x), (y), \ +#define PSC_REG_MDCTL_SET_RESET_ISO(x, y) boot_set_bitfield((x), (y), \ 12, 12) /* MDSTAT */