From patchwork Wed Apr 20 16:14:01 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Griffin X-Patchwork-Id: 66223 Delivered-To: patches@linaro.org Received: by 10.140.93.198 with SMTP id d64csp2540662qge; Wed, 20 Apr 2016 09:14:17 -0700 (PDT) X-Received: by 10.194.74.231 with SMTP id x7mr9408226wjv.60.1461168857745; Wed, 20 Apr 2016 09:14:17 -0700 (PDT) Return-Path: Received: from mail-wm0-x22d.google.com (mail-wm0-x22d.google.com. [2a00:1450:400c:c09::22d]) by mx.google.com with ESMTPS id ji7si6742821wjb.247.2016.04.20.09.14.17 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 20 Apr 2016 09:14:17 -0700 (PDT) Received-SPF: pass (google.com: domain of peter.griffin@linaro.org designates 2a00:1450:400c:c09::22d as permitted sender) client-ip=2a00:1450:400c:c09::22d; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: domain of peter.griffin@linaro.org designates 2a00:1450:400c:c09::22d as permitted sender) smtp.mailfrom=peter.griffin@linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by mail-wm0-x22d.google.com with SMTP id e201so56613313wme.0 for ; Wed, 20 Apr 2016 09:14:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=XgMCwiPjPlkjsxfZoOFFT7c4FigWqTHrcdf/VjPC+7Y=; b=Kg/aWlEGymtkkPFFEt14hWslzv6RDNCWqUAZLqvYOHhiKwugaztokEcfWDgrDCWQMI bwFJsbomxbtV3R1zKxUFnsk03pMpAjksYu1/6Fg9og3+UiQOAu7jHXqgN+VwxZ7iA8kg F96UnvrcKhjBow5XaSrFUvHkgLfFyMns5sYAw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XgMCwiPjPlkjsxfZoOFFT7c4FigWqTHrcdf/VjPC+7Y=; b=NRGK3d2NHy/hiIA0T7TKponZxJkoxcJDjz5dK8t7e5RLfqavKOhlqNIB1ucB71hUtb 3L8uPfVxz6jppB7b2m4DoRzZhDQLakzgV6YFijtKce57uLaC5KVbvdHwARsAJL4yb8fO Bqbf9oRmkaiCpxB2p5pIDDu9oQvDTvJ8s/Y5DanoV6laeTIyxJQaBewgJcBDkv5LyITh 1ihoA5tHvJY9iIz3gLi/0LzUv/q/aIvgDk1t8o6megFslmsc+KEaUuUEKJiFkxVl3eO9 +JqUJc0jSBqQXxZteNqj1wNu+QMmW2y/mP2NiYwfBw9YuF808eYdDymTtFXS/3gdDEYL 9fOg== X-Gm-Message-State: AOPr4FWsBbEwbQtNiaD5qvw3KY+RgHBeGUietLwwPfp5NlYejjjNtUU65e0AkRms0HGumuq56Gs= X-Received: by 10.28.92.69 with SMTP id q66mr10762456wmb.102.1461168857496; Wed, 20 Apr 2016 09:14:17 -0700 (PDT) Return-Path: Received: from localhost.localdomain (cpc84787-aztw28-2-0-cust15.18-1.cable.virginm.net. [82.37.140.16]) by smtp.gmail.com with ESMTPSA id da5sm6353845wjb.25.2016.04.20.09.14.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 20 Apr 2016 09:14:16 -0700 (PDT) From: Peter Griffin To: u-boot@lists.denx.de, albert.u.boot@aribaud.net, sjg@chromium.org, agraf@suse.de, trini@konsulko.com, liming.wang@canonical.com Cc: Peter Griffin Subject: [PATCH 5/7] ARM: hisilicon: hikey: dts: Add pl011 additional clock binding. Date: Wed, 20 Apr 2016 17:14:01 +0100 Message-Id: <1461168843-15610-6-git-send-email-peter.griffin@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1461168843-15610-1-git-send-email-peter.griffin@linaro.org> References: <1461168843-15610-1-git-send-email-peter.griffin@linaro.org> This is a binding which only exists in U-Boot, but is required to get working serial in U-Boot. Signed-off-by: Peter Griffin --- arch/arm/dts/hi6220.dtsi | 5 +++++ 1 file changed, 5 insertions(+) -- 1.9.1 diff --git a/arch/arm/dts/hi6220.dtsi b/arch/arm/dts/hi6220.dtsi index ad1f1eb..a610ccb 100644 --- a/arch/arm/dts/hi6220.dtsi +++ b/arch/arm/dts/hi6220.dtsi @@ -166,6 +166,7 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xf8015000 0x0 0x1000>; interrupts = ; + clock = <19200000>; clocks = <&ao_ctrl HI6220_UART0_PCLK>, <&ao_ctrl HI6220_UART0_PCLK>; clock-names = "uartclk", "apb_pclk"; @@ -175,6 +176,7 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xf7111000 0x0 0x1000>; interrupts = ; + clock = <19200000>; clocks = <&sys_ctrl HI6220_UART1_PCLK>, <&sys_ctrl HI6220_UART1_PCLK>; clock-names = "uartclk", "apb_pclk"; @@ -185,6 +187,7 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xf7112000 0x0 0x1000>; interrupts = ; + clock = <19200000>; clocks = <&sys_ctrl HI6220_UART2_PCLK>, <&sys_ctrl HI6220_UART2_PCLK>; clock-names = "uartclk", "apb_pclk"; @@ -195,6 +198,7 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xf7113000 0x0 0x1000>; interrupts = ; + clock = <19200000>; clocks = <&sys_ctrl HI6220_UART3_PCLK>, <&sys_ctrl HI6220_UART3_PCLK>; clock-names = "uartclk", "apb_pclk"; @@ -204,6 +208,7 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xf7114000 0x0 0x1000>; interrupts = ; + clock = <19200000>; clocks = <&sys_ctrl HI6220_UART4_PCLK>, <&sys_ctrl HI6220_UART4_PCLK>; clock-names = "uartclk", "apb_pclk";