diff --git a/arch/arm/mach-uniphier/board_init.c b/arch/arm/mach-uniphier/board_init.c
index c9d3f28..a1c7541 100644
--- a/arch/arm/mach-uniphier/board_init.c
+++ b/arch/arm/mach-uniphier/board_init.c
@@ -65,6 +65,7 @@ int board_init(void)
 	case SOC_UNIPHIER_SLD3:
 		uniphier_nand_pin_init(true);
 		led_puts("U1");
+		uniphier_sld3_pll_init();
 		uniphier_ld4_clk_init();
 		break;
 #endif
@@ -72,6 +73,7 @@ int board_init(void)
 	case SOC_UNIPHIER_LD4:
 		uniphier_nand_pin_init(true);
 		led_puts("U1");
+		uniphier_ld4_pll_init();
 		uniphier_ld4_clk_init();
 		break;
 #endif
@@ -79,6 +81,7 @@ int board_init(void)
 	case SOC_UNIPHIER_PRO4:
 		uniphier_nand_pin_init(false);
 		led_puts("U1");
+		uniphier_pro4_pll_init();
 		uniphier_pro4_clk_init();
 		break;
 #endif
@@ -86,6 +89,7 @@ int board_init(void)
 	case SOC_UNIPHIER_SLD8:
 		uniphier_nand_pin_init(true);
 		led_puts("U1");
+		uniphier_ld4_pll_init();
 		uniphier_ld4_clk_init();
 		break;
 #endif
diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile
index 1428e0c..b722781 100644
--- a/arch/arm/mach-uniphier/clk/Makefile
+++ b/arch/arm/mach-uniphier/clk/Makefile
@@ -2,10 +2,10 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-$(CONFIG_ARCH_UNIPHIER_SLD3)	+= clk-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD4)		+= clk-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PRO4)	+= clk-pro4.o
-obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= clk-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD3)	+= clk-ld4.o pll-sld3.o dpll-tail.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD4)		+= clk-ld4.o pll-ld4.o dpll-tail.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO4)	+= clk-pro4.o pll-pro4.o dpll-tail.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= clk-ld4.o pll-ld4.o dpll-tail.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= clk-pro5.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= clk-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= clk-pxs2.o
diff --git a/arch/arm/mach-uniphier/pll/pll-spectrum-ld4.c b/arch/arm/mach-uniphier/clk/dpll-tail.c
similarity index 72%
rename from arch/arm/mach-uniphier/pll/pll-spectrum-ld4.c
rename to arch/arm/mach-uniphier/clk/dpll-tail.c
index dc97697..49db555 100644
--- a/arch/arm/mach-uniphier/pll/pll-spectrum-ld4.c
+++ b/arch/arm/mach-uniphier/clk/dpll-tail.c
@@ -6,16 +6,14 @@
 
 #include <linux/io.h>
 
-#include "../init.h"
 #include "../sc-regs.h"
+#include "pll.h"
 
-int uniphier_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd)
+void uniphier_ld4_dpll_ssc_en(void)
 {
 	u32 tmp;
 
 	tmp = readl(SC_DPLLCTRL);
 	tmp |= SC_DPLLCTRL_SSC_EN;
 	writel(tmp, SC_DPLLCTRL);
-
-	return 0;
 }
diff --git a/arch/arm/mach-uniphier/clk/pll-ld4.c b/arch/arm/mach-uniphier/clk/pll-ld4.c
new file mode 100644
index 0000000..b436e7a
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/pll-ld4.c
@@ -0,0 +1,152 @@
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+#include "../sg-regs.h"
+#include "pll.h"
+
+static void upll_init(void)
+{
+	u32 tmp, clk_mode_upll, clk_mode_axosel;
+
+	tmp = readl(SG_PINMON0);
+	clk_mode_upll   = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
+	clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
+
+	/* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
+	tmp = readl(SC_UPLLCTRL);
+	tmp &= ~0x18000000;
+	writel(tmp, SC_UPLLCTRL);
+
+	if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
+		if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
+		    clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
+			/* AXO: 25MHz */
+			tmp &= ~0x07ffffff;
+			tmp |= 0x0228f5c0;
+		} else {
+			/* AXO: default 24.576MHz */
+			tmp &= ~0x07ffffff;
+			tmp |= 0x02328000;
+		}
+	}
+
+	writel(tmp, SC_UPLLCTRL);
+
+	/* set 1 to K_LD(UPLLCTRL.bit[27]) */
+	tmp |= 0x08000000;
+	writel(tmp, SC_UPLLCTRL);
+
+	/* wait 10 usec */
+	udelay(10);
+
+	/* set 1 to SNRT(UPLLCTRL.bit[28]) */
+	tmp |= 0x10000000;
+	writel(tmp, SC_UPLLCTRL);
+}
+
+static void vpll_init(void)
+{
+	u32 tmp, clk_mode_axosel;
+
+	tmp = readl(SG_PINMON0);
+	clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
+
+	/* set 1 to VPLA27WP and VPLA27WP */
+	tmp = readl(SC_VPLL27ACTRL);
+	tmp |= 0x00000001;
+	writel(tmp, SC_VPLL27ACTRL);
+	tmp = readl(SC_VPLL27BCTRL);
+	tmp |= 0x00000001;
+	writel(tmp, SC_VPLL27BCTRL);
+
+	/* Set 0 to VPLA_K_LD and VPLB_K_LD */
+	tmp = readl(SC_VPLL27ACTRL3);
+	tmp &= ~0x10000000;
+	writel(tmp, SC_VPLL27ACTRL3);
+	tmp = readl(SC_VPLL27BCTRL3);
+	tmp &= ~0x10000000;
+	writel(tmp, SC_VPLL27BCTRL3);
+
+	/* Set 0 to VPLA_SNRST and VPLB_SNRST */
+	tmp = readl(SC_VPLL27ACTRL2);
+	tmp &= ~0x10000000;
+	writel(tmp, SC_VPLL27ACTRL2);
+	tmp = readl(SC_VPLL27BCTRL2);
+	tmp &= ~0x10000000;
+	writel(tmp, SC_VPLL27BCTRL2);
+
+	/* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
+	tmp = readl(SC_VPLL27ACTRL2);
+	tmp &= ~0x0000007f;
+	tmp |= 0x00000020;
+	writel(tmp, SC_VPLL27ACTRL2);
+	tmp = readl(SC_VPLL27BCTRL2);
+	tmp &= ~0x0000007f;
+	tmp |= 0x00000020;
+	writel(tmp, SC_VPLL27BCTRL2);
+
+	if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
+	    clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
+		/* AXO: 25MHz */
+		tmp = readl(SC_VPLL27ACTRL3);
+		tmp &= ~0x000fffff;
+		tmp |= 0x00066664;
+		writel(tmp, SC_VPLL27ACTRL3);
+		tmp = readl(SC_VPLL27BCTRL3);
+		tmp &= ~0x000fffff;
+		tmp |= 0x00066664;
+		writel(tmp, SC_VPLL27BCTRL3);
+	} else {
+		/* AXO: default 24.576MHz */
+		tmp = readl(SC_VPLL27ACTRL3);
+		tmp &= ~0x000fffff;
+		tmp |= 0x000f5800;
+		writel(tmp, SC_VPLL27ACTRL3);
+		tmp = readl(SC_VPLL27BCTRL3);
+		tmp &= ~0x000fffff;
+		tmp |= 0x000f5800;
+		writel(tmp, SC_VPLL27BCTRL3);
+	}
+
+	/* Set 1 to VPLA_K_LD and VPLB_K_LD */
+	tmp = readl(SC_VPLL27ACTRL3);
+	tmp |= 0x10000000;
+	writel(tmp, SC_VPLL27ACTRL3);
+	tmp = readl(SC_VPLL27BCTRL3);
+	tmp |= 0x10000000;
+	writel(tmp, SC_VPLL27BCTRL3);
+
+	/* wait 10 usec */
+	udelay(10);
+
+	/* Set 0 to VPLA_SNRST and VPLB_SNRST */
+	tmp = readl(SC_VPLL27ACTRL2);
+	tmp |= 0x10000000;
+	writel(tmp, SC_VPLL27ACTRL2);
+	tmp = readl(SC_VPLL27BCTRL2);
+	tmp |= 0x10000000;
+	writel(tmp, SC_VPLL27BCTRL2);
+
+	/* set 0 to VPLA27WP and VPLA27WP */
+	tmp = readl(SC_VPLL27ACTRL);
+	tmp &= ~0x00000001;
+	writel(tmp, SC_VPLL27ACTRL);
+	tmp = readl(SC_VPLL27BCTRL);
+	tmp |= ~0x00000001;
+	writel(tmp, SC_VPLL27BCTRL);
+}
+
+void uniphier_ld4_pll_init(void)
+{
+	upll_init();
+	vpll_init();
+	uniphier_ld4_dpll_ssc_en();
+}
diff --git a/arch/arm/mach-uniphier/clk/pll-pro4.c b/arch/arm/mach-uniphier/clk/pll-pro4.c
new file mode 100644
index 0000000..10bc809
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/pll-pro4.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc-regs.h"
+#include "../sg-regs.h"
+#include "pll.h"
+
+static void vpll_init(void)
+{
+	u32 tmp, clk_mode_axosel;
+
+	/* Set VPLL27A &  VPLL27B */
+	tmp = readl(SG_PINMON0);
+	clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
+
+	/* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */
+	if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
+	    clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ)
+		return;
+
+	/* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
+	tmp = readl(SC_VPLL27ACTRL);
+	tmp |= 0x00000001;
+	writel(tmp, SC_VPLL27ACTRL);
+	tmp = readl(SC_VPLL27BCTRL);
+	tmp |= 0x00000001;
+	writel(tmp, SC_VPLL27BCTRL);
+
+	/* Unset VPLA_K_LD and VPLB_K_LD bit */
+	tmp = readl(SC_VPLL27ACTRL3);
+	tmp &= ~0x10000000;
+	writel(tmp, SC_VPLL27ACTRL3);
+	tmp = readl(SC_VPLL27BCTRL3);
+	tmp &= ~0x10000000;
+	writel(tmp, SC_VPLL27BCTRL3);
+
+	/* Set VPLA_M and VPLB_M to 0x20 */
+	tmp = readl(SC_VPLL27ACTRL2);
+	tmp &= ~0x0000007f;
+	tmp |= 0x00000020;
+	writel(tmp, SC_VPLL27ACTRL2);
+	tmp = readl(SC_VPLL27BCTRL2);
+	tmp &= ~0x0000007f;
+	tmp |= 0x00000020;
+	writel(tmp, SC_VPLL27BCTRL2);
+
+	if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
+	    clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) {
+		/* Set VPLA_K and VPLB_K for AXO: 25MHz */
+		tmp = readl(SC_VPLL27ACTRL3);
+		tmp &= ~0x000fffff;
+		tmp |= 0x00066666;
+		writel(tmp, SC_VPLL27ACTRL3);
+		tmp = readl(SC_VPLL27BCTRL3);
+		tmp &= ~0x000fffff;
+		tmp |= 0x00066666;
+		writel(tmp, SC_VPLL27BCTRL3);
+	} else {
+		/* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */
+		tmp = readl(SC_VPLL27ACTRL3);
+		tmp &= ~0x000fffff;
+		tmp |= 0x000f5800;
+		writel(tmp, SC_VPLL27ACTRL3);
+		tmp = readl(SC_VPLL27BCTRL3);
+		tmp &= ~0x000fffff;
+		tmp |= 0x000f5800;
+		writel(tmp, SC_VPLL27BCTRL3);
+	}
+
+	/* wait 1 usec */
+	udelay(1);
+
+	/* Set VPLA_K_LD and VPLB_K_LD to load K parameters */
+	tmp = readl(SC_VPLL27ACTRL3);
+	tmp |= 0x10000000;
+	writel(tmp, SC_VPLL27ACTRL3);
+	tmp = readl(SC_VPLL27BCTRL3);
+	tmp |= 0x10000000;
+	writel(tmp, SC_VPLL27BCTRL3);
+
+	/* Unset VPLA_SNRST and VPLB_SNRST bit */
+	tmp = readl(SC_VPLL27ACTRL2);
+	tmp |= 0x10000000;
+	writel(tmp, SC_VPLL27ACTRL2);
+	tmp = readl(SC_VPLL27BCTRL2);
+	tmp |= 0x10000000;
+	writel(tmp, SC_VPLL27BCTRL2);
+
+	/* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
+	tmp = readl(SC_VPLL27ACTRL);
+	tmp &= ~0x00000001;
+	writel(tmp, SC_VPLL27ACTRL);
+	tmp = readl(SC_VPLL27BCTRL);
+	tmp &= ~0x00000001;
+	writel(tmp, SC_VPLL27BCTRL);
+}
+
+void uniphier_pro4_pll_init(void)
+{
+	vpll_init();
+	uniphier_ld4_dpll_ssc_en();
+}
diff --git a/arch/arm/mach-uniphier/clk/pll-sld3.c b/arch/arm/mach-uniphier/clk/pll-sld3.c
new file mode 100644
index 0000000..37a7c12
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/pll-sld3.c
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include "../init.h"
+#include "pll.h"
+
+void uniphier_sld3_pll_init(void)
+{
+	uniphier_ld4_dpll_ssc_en();
+}
diff --git a/arch/arm/mach-uniphier/clk/pll.h b/arch/arm/mach-uniphier/clk/pll.h
new file mode 100644
index 0000000..ef0f722
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/pll.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef MACH_PLL_H
+#define MACH_PLL_H
+
+void uniphier_ld4_dpll_ssc_en(void);
+
+#endif /* MACH_PLL_H */
diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h
index 1dc53d5..d8f5b49 100644
--- a/arch/arm/mach-uniphier/init.h
+++ b/arch/arm/mach-uniphier/init.h
@@ -80,13 +80,10 @@ int memconf_init(const struct uniphier_board_data *bd);
 int uniphier_sld3_memconf_init(const struct uniphier_board_data *bd);
 int uniphier_pxs2_memconf_init(const struct uniphier_board_data *bd);
 
-int uniphier_sld3_pll_init(const struct uniphier_board_data *bd);
-int uniphier_ld4_pll_init(const struct uniphier_board_data *bd);
-int uniphier_pro4_pll_init(const struct uniphier_board_data *bd);
-int uniphier_sld8_pll_init(const struct uniphier_board_data *bd);
-
-int uniphier_sld3_enable_dpll_ssc(const struct uniphier_board_data *bd);
-int uniphier_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd);
+int uniphier_sld3_dpll_init(const struct uniphier_board_data *bd);
+int uniphier_ld4_dpll_init(const struct uniphier_board_data *bd);
+int uniphier_pro4_dpll_init(const struct uniphier_board_data *bd);
+int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd);
 
 int uniphier_ld4_early_clk_init(const struct uniphier_board_data *bd);
 int uniphier_pro5_early_clk_init(const struct uniphier_board_data *bd);
@@ -101,6 +98,10 @@ int uniphier_pxs2_umc_init(const struct uniphier_board_data *bd);
 int uniphier_ld20_umc_init(const struct uniphier_board_data *bd);
 int uniphier_ld11_umc_init(const struct uniphier_board_data *bd);
 
+void uniphier_sld3_pll_init(void);
+void uniphier_ld4_pll_init(void);
+void uniphier_pro4_pll_init(void);
+
 void uniphier_ld4_clk_init(void);
 void uniphier_pro4_clk_init(void);
 void uniphier_pro5_clk_init(void);
diff --git a/arch/arm/mach-uniphier/init/init-ld4.c b/arch/arm/mach-uniphier/init/init-ld4.c
index b1c9b5d..34d70f6 100644
--- a/arch/arm/mach-uniphier/init/init-ld4.c
+++ b/arch/arm/mach-uniphier/init/init-ld4.c
@@ -19,7 +19,7 @@ int uniphier_ld4_init(const struct uniphier_board_data *bd)
 
 	support_card_reset();
 
-	uniphier_ld4_pll_init(bd);
+	uniphier_ld4_dpll_init(bd);
 
 	support_card_init();
 
@@ -53,9 +53,5 @@ int uniphier_ld4_init(const struct uniphier_board_data *bd)
 
 	led_puts("L5");
 
-	uniphier_ld4_enable_dpll_ssc(bd);
-
-	led_puts("L6");
-
 	return 0;
 }
diff --git a/arch/arm/mach-uniphier/init/init-pro4.c b/arch/arm/mach-uniphier/init/init-pro4.c
index 3528d84..1b402f4 100644
--- a/arch/arm/mach-uniphier/init/init-pro4.c
+++ b/arch/arm/mach-uniphier/init/init-pro4.c
@@ -16,7 +16,7 @@ int uniphier_pro4_init(const struct uniphier_board_data *bd)
 
 	support_card_reset();
 
-	uniphier_pro4_pll_init(bd);
+	uniphier_pro4_dpll_init(bd);
 
 	support_card_init();
 
@@ -50,9 +50,5 @@ int uniphier_pro4_init(const struct uniphier_board_data *bd)
 
 	led_puts("L5");
 
-	uniphier_ld4_enable_dpll_ssc(bd);
-
-	led_puts("L6");
-
 	return 0;
 }
diff --git a/arch/arm/mach-uniphier/init/init-sld3.c b/arch/arm/mach-uniphier/init/init-sld3.c
index 1ee57ec..1022a0b 100644
--- a/arch/arm/mach-uniphier/init/init-sld3.c
+++ b/arch/arm/mach-uniphier/init/init-sld3.c
@@ -18,7 +18,7 @@ int uniphier_sld3_init(const struct uniphier_board_data *bd)
 
 	support_card_reset();
 
-	uniphier_sld3_pll_init(bd);
+	uniphier_sld3_dpll_init(bd);
 
 	support_card_init();
 
@@ -43,9 +43,5 @@ int uniphier_sld3_init(const struct uniphier_board_data *bd)
 
 	led_puts("L5");
 
-	uniphier_sld3_enable_dpll_ssc(bd);
-
-	led_puts("L6");
-
 	return 0;
 }
diff --git a/arch/arm/mach-uniphier/init/init-sld8.c b/arch/arm/mach-uniphier/init/init-sld8.c
index 07c6d60..3553bbf 100644
--- a/arch/arm/mach-uniphier/init/init-sld8.c
+++ b/arch/arm/mach-uniphier/init/init-sld8.c
@@ -19,7 +19,7 @@ int uniphier_sld8_init(const struct uniphier_board_data *bd)
 
 	support_card_reset();
 
-	uniphier_sld8_pll_init(bd);
+	uniphier_sld8_dpll_init(bd);
 
 	support_card_init();
 
@@ -53,9 +53,5 @@ int uniphier_sld8_init(const struct uniphier_board_data *bd)
 
 	led_puts("L5");
 
-	uniphier_ld4_enable_dpll_ssc(bd);
-
-	led_puts("L6");
-
 	return 0;
 }
diff --git a/arch/arm/mach-uniphier/pll/Makefile b/arch/arm/mach-uniphier/pll/Makefile
index 63f169c..db22ba4 100644
--- a/arch/arm/mach-uniphier/pll/Makefile
+++ b/arch/arm/mach-uniphier/pll/Makefile
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-$(CONFIG_ARCH_UNIPHIER_SLD3)	+= pll-init-sld3.o pll-spectrum-sld3.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD4)		+= pll-init-ld4.o pll-spectrum-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PRO4)	+= pll-init-pro4.o pll-spectrum-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= pll-init-sld8.o pll-spectrum-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD3)	+= pll-init-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD4)		+= pll-init-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO4)	+= pll-init-pro4.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= pll-init-sld8.o
diff --git a/arch/arm/mach-uniphier/pll/pll-init-ld4.c b/arch/arm/mach-uniphier/pll/pll-init-ld4.c
index 57c1d9f..30fc22e 100644
--- a/arch/arm/mach-uniphier/pll/pll-init-ld4.c
+++ b/arch/arm/mach-uniphier/pll/pll-init-ld4.c
@@ -10,12 +10,12 @@
 
 #include "../init.h"
 #include "../sc-regs.h"
-#include "../sg-regs.h"
 
 #undef DPLL_SSC_RATE_1PER
 
-static int dpll_init(unsigned int dram_freq)
+int uniphier_ld4_dpll_init(const struct uniphier_board_data *bd)
 {
+	unsigned int dram_freq = bd->dram_freq;
 	u32 tmp;
 
 	/*
@@ -48,157 +48,8 @@ static int dpll_init(unsigned int dram_freq)
 	tmp |= SC_DPLLCTRL2_NRSTDS;
 	writel(tmp, SC_DPLLCTRL2);
 
-	return 0;
-}
-
-static void upll_init(void)
-{
-	u32 tmp, clk_mode_upll, clk_mode_axosel;
-
-	tmp = readl(SG_PINMON0);
-	clk_mode_upll   = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
-	clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
-
-	/* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
-	tmp = readl(SC_UPLLCTRL);
-	tmp &= ~0x18000000;
-	writel(tmp, SC_UPLLCTRL);
-
-	if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
-		if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
-		    clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
-			/* AXO: 25MHz */
-			tmp &= ~0x07ffffff;
-			tmp |= 0x0228f5c0;
-		} else {
-			/* AXO: default 24.576MHz */
-			tmp &= ~0x07ffffff;
-			tmp |= 0x02328000;
-		}
-	}
-
-	writel(tmp, SC_UPLLCTRL);
-
-	/* set 1 to K_LD(UPLLCTRL.bit[27]) */
-	tmp |= 0x08000000;
-	writel(tmp, SC_UPLLCTRL);
-
-	/* wait 10 usec */
-	udelay(10);
-
-	/* set 1 to SNRT(UPLLCTRL.bit[28]) */
-	tmp |= 0x10000000;
-	writel(tmp, SC_UPLLCTRL);
-}
-
-static void vpll_init(void)
-{
-	u32 tmp, clk_mode_axosel;
-
-	tmp = readl(SG_PINMON0);
-	clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
-
-	/* set 1 to VPLA27WP and VPLA27WP */
-	tmp = readl(SC_VPLL27ACTRL);
-	tmp |= 0x00000001;
-	writel(tmp, SC_VPLL27ACTRL);
-	tmp = readl(SC_VPLL27BCTRL);
-	tmp |= 0x00000001;
-	writel(tmp, SC_VPLL27BCTRL);
-
-	/* Set 0 to VPLA_K_LD and VPLB_K_LD */
-	tmp = readl(SC_VPLL27ACTRL3);
-	tmp &= ~0x10000000;
-	writel(tmp, SC_VPLL27ACTRL3);
-	tmp = readl(SC_VPLL27BCTRL3);
-	tmp &= ~0x10000000;
-	writel(tmp, SC_VPLL27BCTRL3);
-
-	/* Set 0 to VPLA_SNRST and VPLB_SNRST */
-	tmp = readl(SC_VPLL27ACTRL2);
-	tmp &= ~0x10000000;
-	writel(tmp, SC_VPLL27ACTRL2);
-	tmp = readl(SC_VPLL27BCTRL2);
-	tmp &= ~0x10000000;
-	writel(tmp, SC_VPLL27BCTRL2);
-
-	/* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
-	tmp = readl(SC_VPLL27ACTRL2);
-	tmp &= ~0x0000007f;
-	tmp |= 0x00000020;
-	writel(tmp, SC_VPLL27ACTRL2);
-	tmp = readl(SC_VPLL27BCTRL2);
-	tmp &= ~0x0000007f;
-	tmp |= 0x00000020;
-	writel(tmp, SC_VPLL27BCTRL2);
-
-	if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
-	    clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
-		/* AXO: 25MHz */
-		tmp = readl(SC_VPLL27ACTRL3);
-		tmp &= ~0x000fffff;
-		tmp |= 0x00066664;
-		writel(tmp, SC_VPLL27ACTRL3);
-		tmp = readl(SC_VPLL27BCTRL3);
-		tmp &= ~0x000fffff;
-		tmp |= 0x00066664;
-		writel(tmp, SC_VPLL27BCTRL3);
-	} else {
-		/* AXO: default 24.576MHz */
-		tmp = readl(SC_VPLL27ACTRL3);
-		tmp &= ~0x000fffff;
-		tmp |= 0x000f5800;
-		writel(tmp, SC_VPLL27ACTRL3);
-		tmp = readl(SC_VPLL27BCTRL3);
-		tmp &= ~0x000fffff;
-		tmp |= 0x000f5800;
-		writel(tmp, SC_VPLL27BCTRL3);
-	}
-
-	/* Set 1 to VPLA_K_LD and VPLB_K_LD */
-	tmp = readl(SC_VPLL27ACTRL3);
-	tmp |= 0x10000000;
-	writel(tmp, SC_VPLL27ACTRL3);
-	tmp = readl(SC_VPLL27BCTRL3);
-	tmp |= 0x10000000;
-	writel(tmp, SC_VPLL27BCTRL3);
-
-	/* wait 10 usec */
-	udelay(10);
-
-	/* Set 0 to VPLA_SNRST and VPLB_SNRST */
-	tmp = readl(SC_VPLL27ACTRL2);
-	tmp |= 0x10000000;
-	writel(tmp, SC_VPLL27ACTRL2);
-	tmp = readl(SC_VPLL27BCTRL2);
-	tmp |= 0x10000000;
-	writel(tmp, SC_VPLL27BCTRL2);
-
-	/* set 0 to VPLA27WP and VPLA27WP */
-	tmp = readl(SC_VPLL27ACTRL);
-	tmp &= ~0x00000001;
-	writel(tmp, SC_VPLL27ACTRL);
-	tmp = readl(SC_VPLL27BCTRL);
-	tmp |= ~0x00000001;
-	writel(tmp, SC_VPLL27BCTRL);
-}
-
-int uniphier_ld4_pll_init(const struct uniphier_board_data *bd)
-{
-	int ret;
-
-	ret = dpll_init(bd->dram_freq);
-	if (ret)
-		return ret;
-	upll_init();
-	vpll_init();
-
-	/*
-	 * Wait 500 usec until dpll get stable
-	 * We wait 10 usec in upll_init() and vpll_init()
-	 * so 20 usec can be saved here.
-	 */
-	udelay(480);
+	/* Wait 500 usec until dpll gets stable */
+	udelay(500);
 
 	return 0;
 }
diff --git a/arch/arm/mach-uniphier/pll/pll-init-pro4.c b/arch/arm/mach-uniphier/pll/pll-init-pro4.c
index a7e4e0e..c468a09 100644
--- a/arch/arm/mach-uniphier/pll/pll-init-pro4.c
+++ b/arch/arm/mach-uniphier/pll/pll-init-pro4.c
@@ -10,12 +10,12 @@
 
 #include "../init.h"
 #include "../sc-regs.h"
-#include "../sg-regs.h"
 
 #undef DPLL_SSC_RATE_1PER
 
-static int dpll_init(unsigned int dram_freq)
+int uniphier_pro4_dpll_init(const struct uniphier_board_data *bd)
 {
+	unsigned int dram_freq = bd->dram_freq;
 	u32 tmp;
 
 	/*
@@ -52,113 +52,8 @@ static int dpll_init(unsigned int dram_freq)
 	tmp |= SC_DPLLCTRL2_NRSTDS;
 	writel(tmp, SC_DPLLCTRL2);
 
-	return 0;
-}
-
-static void vpll_init(void)
-{
-	u32 tmp, clk_mode_axosel;
-
-	/* Set VPLL27A &  VPLL27B */
-	tmp = readl(SG_PINMON0);
-	clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
-
-	/* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */
-	if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
-	    clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ)
-		return;
-
-	/* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
-	tmp = readl(SC_VPLL27ACTRL);
-	tmp |= 0x00000001;
-	writel(tmp, SC_VPLL27ACTRL);
-	tmp = readl(SC_VPLL27BCTRL);
-	tmp |= 0x00000001;
-	writel(tmp, SC_VPLL27BCTRL);
-
-	/* Unset VPLA_K_LD and VPLB_K_LD bit */
-	tmp = readl(SC_VPLL27ACTRL3);
-	tmp &= ~0x10000000;
-	writel(tmp, SC_VPLL27ACTRL3);
-	tmp = readl(SC_VPLL27BCTRL3);
-	tmp &= ~0x10000000;
-	writel(tmp, SC_VPLL27BCTRL3);
-
-	/* Set VPLA_M and VPLB_M to 0x20 */
-	tmp = readl(SC_VPLL27ACTRL2);
-	tmp &= ~0x0000007f;
-	tmp |= 0x00000020;
-	writel(tmp, SC_VPLL27ACTRL2);
-	tmp = readl(SC_VPLL27BCTRL2);
-	tmp &= ~0x0000007f;
-	tmp |= 0x00000020;
-	writel(tmp, SC_VPLL27BCTRL2);
-
-	if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
-	    clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) {
-		/* Set VPLA_K and VPLB_K for AXO: 25MHz */
-		tmp = readl(SC_VPLL27ACTRL3);
-		tmp &= ~0x000fffff;
-		tmp |= 0x00066666;
-		writel(tmp, SC_VPLL27ACTRL3);
-		tmp = readl(SC_VPLL27BCTRL3);
-		tmp &= ~0x000fffff;
-		tmp |= 0x00066666;
-		writel(tmp, SC_VPLL27BCTRL3);
-	} else {
-		/* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */
-		tmp = readl(SC_VPLL27ACTRL3);
-		tmp &= ~0x000fffff;
-		tmp |= 0x000f5800;
-		writel(tmp, SC_VPLL27ACTRL3);
-		tmp = readl(SC_VPLL27BCTRL3);
-		tmp &= ~0x000fffff;
-		tmp |= 0x000f5800;
-		writel(tmp, SC_VPLL27BCTRL3);
-	}
-
-	/* wait 1 usec */
-	udelay(1);
-
-	/* Set VPLA_K_LD and VPLB_K_LD to load K parameters */
-	tmp = readl(SC_VPLL27ACTRL3);
-	tmp |= 0x10000000;
-	writel(tmp, SC_VPLL27ACTRL3);
-	tmp = readl(SC_VPLL27BCTRL3);
-	tmp |= 0x10000000;
-	writel(tmp, SC_VPLL27BCTRL3);
-
-	/* Unset VPLA_SNRST and VPLB_SNRST bit */
-	tmp = readl(SC_VPLL27ACTRL2);
-	tmp |= 0x10000000;
-	writel(tmp, SC_VPLL27ACTRL2);
-	tmp = readl(SC_VPLL27BCTRL2);
-	tmp |= 0x10000000;
-	writel(tmp, SC_VPLL27BCTRL2);
-
-	/* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
-	tmp = readl(SC_VPLL27ACTRL);
-	tmp &= ~0x00000001;
-	writel(tmp, SC_VPLL27ACTRL);
-	tmp = readl(SC_VPLL27BCTRL);
-	tmp &= ~0x00000001;
-	writel(tmp, SC_VPLL27BCTRL);
-}
-
-int uniphier_pro4_pll_init(const struct uniphier_board_data *bd)
-{
-	int ret;
-
-	ret = dpll_init(bd->dram_freq);
-	if (ret)
-		return ret;
-	vpll_init();
-
-	/*
-	 * Wait 500 usec until dpll get stable
-	 * We wait 1 usec in vpll_init() so 1 usec can be saved here.
-	 */
-	udelay(499);
+	/* Wait until dpll gets stable */
+	udelay(500);
 
 	return 0;
 }
diff --git a/arch/arm/mach-uniphier/pll/pll-init-sld3.c b/arch/arm/mach-uniphier/pll/pll-init-sld3.c
index 5b4f2e3..0eb310c 100644
--- a/arch/arm/mach-uniphier/pll/pll-init-sld3.c
+++ b/arch/arm/mach-uniphier/pll/pll-init-sld3.c
@@ -6,7 +6,7 @@
 
 #include "../init.h"
 
-int uniphier_sld3_pll_init(const struct uniphier_board_data *bd)
+int uniphier_sld3_dpll_init(const struct uniphier_board_data *bd)
 {
 	/* add pll init code here */
 	return 0;
diff --git a/arch/arm/mach-uniphier/pll/pll-init-sld8.c b/arch/arm/mach-uniphier/pll/pll-init-sld8.c
index 8b6a67c..877b897 100644
--- a/arch/arm/mach-uniphier/pll/pll-init-sld8.c
+++ b/arch/arm/mach-uniphier/pll/pll-init-sld8.c
@@ -9,9 +9,8 @@
 
 #include "../init.h"
 #include "../sc-regs.h"
-#include "../sg-regs.h"
 
-static void dpll_init(void)
+int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd)
 {
 	u32 tmp;
 	/*
@@ -54,152 +53,9 @@ static void dpll_init(void)
 	tmp &= ~0xefffffff;
 	tmp |= 0x0cfeb851;
 	writel(tmp, SC_DPLLCTRL2);
-}
-
-static void upll_init(void)
-{
-	u32 tmp, clk_mode_upll, clk_mode_axosel;
-
-	tmp = readl(SG_PINMON0);
-	clk_mode_upll   = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
-	clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
-
-	/* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
-	tmp = readl(SC_UPLLCTRL);
-	tmp &= ~0x18000000;
-	writel(tmp, SC_UPLLCTRL);
-
-	if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
-		if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
-		    clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
-			/* AXO: 25MHz */
-			tmp &= ~0x07ffffff;
-			tmp |= 0x0228f5c0;
-		} else {
-			/* AXO: default 24.576MHz */
-			tmp &= ~0x07ffffff;
-			tmp |= 0x02328000;
-		}
-	}
-
-	writel(tmp, SC_UPLLCTRL);
-
-	/* set 1 to K_LD(UPLLCTRL.bit[27]) */
-	tmp |= 0x08000000;
-	writel(tmp, SC_UPLLCTRL);
-
-	/* wait 10 usec */
-	udelay(10);
-
-	/* set 1 to SNRT(UPLLCTRL.bit[28]) */
-	tmp |= 0x10000000;
-	writel(tmp, SC_UPLLCTRL);
-}
-
-static void vpll_init(void)
-{
-	u32 tmp, clk_mode_axosel;
-
-	tmp = readl(SG_PINMON0);
-	clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
 
-	/* set 1 to VPLA27WP and VPLA27WP */
-	tmp = readl(SC_VPLL27ACTRL);
-	tmp |= 0x00000001;
-	writel(tmp, SC_VPLL27ACTRL);
-	tmp = readl(SC_VPLL27BCTRL);
-	tmp |= 0x00000001;
-	writel(tmp, SC_VPLL27BCTRL);
-
-	/* Set 0 to VPLA_K_LD and VPLB_K_LD */
-	tmp = readl(SC_VPLL27ACTRL3);
-	tmp &= ~0x10000000;
-	writel(tmp, SC_VPLL27ACTRL3);
-	tmp = readl(SC_VPLL27BCTRL3);
-	tmp &= ~0x10000000;
-	writel(tmp, SC_VPLL27BCTRL3);
-
-	/* Set 0 to VPLA_SNRST and VPLB_SNRST */
-	tmp = readl(SC_VPLL27ACTRL2);
-	tmp &= ~0x10000000;
-	writel(tmp, SC_VPLL27ACTRL2);
-	tmp = readl(SC_VPLL27BCTRL2);
-	tmp &= ~0x10000000;
-	writel(tmp, SC_VPLL27BCTRL2);
-
-	/* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
-	tmp = readl(SC_VPLL27ACTRL2);
-	tmp &= ~0x0000007f;
-	tmp |= 0x00000020;
-	writel(tmp, SC_VPLL27ACTRL2);
-	tmp = readl(SC_VPLL27BCTRL2);
-	tmp &= ~0x0000007f;
-	tmp |= 0x00000020;
-	writel(tmp, SC_VPLL27BCTRL2);
-
-	if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
-	    clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
-		/* AXO: 25MHz */
-		tmp = readl(SC_VPLL27ACTRL3);
-		tmp &= ~0x000fffff;
-		tmp |= 0x00066664;
-		writel(tmp, SC_VPLL27ACTRL3);
-		tmp = readl(SC_VPLL27BCTRL3);
-		tmp &= ~0x000fffff;
-		tmp |= 0x00066664;
-		writel(tmp, SC_VPLL27BCTRL3);
-	} else {
-		/* AXO: default 24.576MHz */
-		tmp = readl(SC_VPLL27ACTRL3);
-		tmp &= ~0x000fffff;
-		tmp |= 0x000f5800;
-		writel(tmp, SC_VPLL27ACTRL3);
-		tmp = readl(SC_VPLL27BCTRL3);
-		tmp &= ~0x000fffff;
-		tmp |= 0x000f5800;
-		writel(tmp, SC_VPLL27BCTRL3);
-	}
-
-	/* Set 1 to VPLA_K_LD and VPLB_K_LD */
-	tmp = readl(SC_VPLL27ACTRL3);
-	tmp |= 0x10000000;
-	writel(tmp, SC_VPLL27ACTRL3);
-	tmp = readl(SC_VPLL27BCTRL3);
-	tmp |= 0x10000000;
-	writel(tmp, SC_VPLL27BCTRL3);
-
-	/* wait 10 usec */
-	udelay(10);
-
-	/* Set 0 to VPLA_SNRST and VPLB_SNRST */
-	tmp = readl(SC_VPLL27ACTRL2);
-	tmp |= 0x10000000;
-	writel(tmp, SC_VPLL27ACTRL2);
-	tmp = readl(SC_VPLL27BCTRL2);
-	tmp |= 0x10000000;
-	writel(tmp, SC_VPLL27BCTRL2);
-
-	/* set 0 to VPLA27WP and VPLA27WP */
-	tmp = readl(SC_VPLL27ACTRL);
-	tmp &= ~0x00000001;
-	writel(tmp, SC_VPLL27ACTRL);
-	tmp = readl(SC_VPLL27BCTRL);
-	tmp |= ~0x00000001;
-	writel(tmp, SC_VPLL27BCTRL);
-}
-
-int uniphier_sld8_pll_init(const struct uniphier_board_data *bd)
-{
-	dpll_init();
-	upll_init();
-	vpll_init();
-
-	/*
-	 * Wait 500 usec until dpll get stable
-	 * We wait 10 usec in upll_init() and vpll_init()
-	 * so 20 usec can be saved here.
-	 */
-	udelay(480);
+	/* Wait 500 usec until dpll gets stable */
+	udelay(500);
 
 	return 0;
 }
diff --git a/arch/arm/mach-uniphier/pll/pll-spectrum-sld3.c b/arch/arm/mach-uniphier/pll/pll-spectrum-sld3.c
deleted file mode 100644
index ff09a92..0000000
--- a/arch/arm/mach-uniphier/pll/pll-spectrum-sld3.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-
-#include "../init.h"
-#include "../sc-regs.h"
-
-int uniphier_sld3_enable_dpll_ssc(const struct uniphier_board_data *bd)
-{
-	u32 tmp;
-
-	tmp = readl(SC_DPLLCTRL);
-	tmp |= SC_DPLLCTRL_SSC_EN;
-	writel(tmp, SC_DPLLCTRL);
-
-	return 0;
-}
