From patchwork Fri Sep 23 15:10:01 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep Holla X-Patchwork-Id: 76900 Delivered-To: patch@linaro.org Received: by 10.140.106.72 with SMTP id d66csp37932qgf; Fri, 23 Sep 2016 13:13:16 -0700 (PDT) X-Received: by 10.28.38.193 with SMTP id m184mr4106213wmm.38.1474661596358; Fri, 23 Sep 2016 13:13:16 -0700 (PDT) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id hx4si8915429wjb.258.2016.09.23.13.13.16; Fri, 23 Sep 2016 13:13:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C99DDB38B4; Fri, 23 Sep 2016 22:12:41 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id QCx9FzwtMGKj; Fri, 23 Sep 2016 22:12:41 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 25A72B38CB; Fri, 23 Sep 2016 22:12:21 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6E0B5A76FC for ; Fri, 23 Sep 2016 17:15:18 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ztrdnSRzLfcW for ; Fri, 23 Sep 2016 17:15:18 +0200 (CEST) X-Greylist: delayed 305 seconds by postgrey-1.34 at theia; Fri, 23 Sep 2016 17:15:15 CEST X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from foss.arm.com (foss.arm.com [217.140.101.70]) by theia.denx.de (Postfix) with ESMTP id 15954A76F9 for ; Fri, 23 Sep 2016 17:15:15 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 65A1214; Fri, 23 Sep 2016 08:10:09 -0700 (PDT) Received: from e107155-lin.cambridge.arm.com (e107155-lin.cambridge.arm.com [10.1.210.28]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 1DDCE3F251; Fri, 23 Sep 2016 08:10:07 -0700 (PDT) From: Sudeep Holla To: u-boot@lists.denx.de Date: Fri, 23 Sep 2016 16:10:01 +0100 Message-Id: <1474643401-13624-1-git-send-email-sudeep.holla@arm.com> X-Mailer: git-send-email 2.7.4 X-Mailman-Approved-At: Fri, 23 Sep 2016 22:11:28 +0200 Cc: Nicolas Pitre , Jon Medhurst , Lorenzo Pieralisi , Marc Zyngier , Liviu Dudau , Sudeep Holla Subject: [U-Boot] [PATCH] vexpress: disable cci ace slave ports when booting in non-sec/hyp mode X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Commit f225d39d3093 ("vexpress: Check TC2 firmware support before defaulting to nonsec booting") added support to check if the firmware on TC2 is configured appropriately before booting in nonsec/hyp mode. However when booting in non-secure/hyp mode, CCI control must be done in secure firmware and can't be done in non-secure/hyp mode. In order to ensure that, this patch disables the cci slave port inteface so that it is not accessed at all. Cc: Jon Medhurst Signed-off-by: Sudeep Holla --- board/armltd/vexpress/vexpress_tc2.c | 47 ++++++++++++++++++++++++++++++++++++ configs/vexpress_ca15_tc2_defconfig | 1 + 2 files changed, 48 insertions(+) Hi, This change is needed to avoid the kernel panic while attempting to access CCI ports when booting in non-sec/HYP mode. The kernel patches to fix this are available @[1] Regards, Sudeep [1] http://www.spinics.net/lists/arm-kernel/msg533715.html -- 2.7.4 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/board/armltd/vexpress/vexpress_tc2.c b/board/armltd/vexpress/vexpress_tc2.c index ebb41a8833ab..25bbba7a8590 100644 --- a/board/armltd/vexpress/vexpress_tc2.c +++ b/board/armltd/vexpress/vexpress_tc2.c @@ -8,6 +8,9 @@ */ #include +#include +#include +#include #define SCC_BASE 0x7fff0000 @@ -31,3 +34,47 @@ bool armv7_boot_nonsec_default(void) return (readl((u32 *)(SCC_BASE + 0x700)) & ((1 << 12) | (1 << 13))) == 0; #endif } + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *fdt, bd_t *bd) +{ + int offset, tmp, len; + const struct fdt_property *prop; + const char *cci_compatible = "arm,cci-400-ctrl-if"; + + if (!armv7_boot_nonsec_default()) + return 0; /* Do nothing */ + + offset = fdt_path_offset(fdt, "/cpus"); + if (offset < 0) { + printf("couldn't find /cpus\n"); + return offset; + } + + /* delete cci-control-port in each cpu node */ + for (tmp = fdt_first_subnode(fdt, offset); tmp >= 0; + tmp = fdt_next_subnode(fdt, tmp)) + fdt_delprop(fdt, tmp, "cci-control-port"); + + /* disable all ace cci slave ports */ + offset = fdt_node_offset_by_prop_value(fdt, offset, "compatible", + cci_compatible, 20); + while (offset > 0) { + prop = fdt_get_property(fdt, offset, "interface-type", + &len); + if (!prop) + continue; + if (len < 4) + continue; + if (strcmp(prop->data, "ace")) + continue; + + fdt_setprop_string(fdt, offset, "status", "disabled"); + + offset = fdt_node_offset_by_prop_value(fdt, offset, "compatible", + cci_compatible, 20); + } + + return 0; +} +#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/configs/vexpress_ca15_tc2_defconfig b/configs/vexpress_ca15_tc2_defconfig index 2f141dda06c6..5154803b7c65 100644 --- a/configs/vexpress_ca15_tc2_defconfig +++ b/configs/vexpress_ca15_tc2_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_VEXPRESS_CA15_TC2=y +CONFIG_OF_BOARD_SETUP=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set