From patchwork Fri Dec 9 06:46:39 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 87386 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp158697qgi; Thu, 8 Dec 2016 22:46:59 -0800 (PST) X-Received: by 10.194.98.208 with SMTP id ek16mr78784044wjb.94.1481266019204; Thu, 08 Dec 2016 22:46:59 -0800 (PST) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id th3si32659094wjb.57.2016.12.08.22.46.58; Thu, 08 Dec 2016 22:46:59 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 58039A75B7; Fri, 9 Dec 2016 07:46:58 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Tf63DnQGPqcw; Fri, 9 Dec 2016 07:46:58 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E0671A75A9; Fri, 9 Dec 2016 07:46:57 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CB320A75A9 for ; Fri, 9 Dec 2016 07:46:53 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id FDugw_YnHLpa for ; Fri, 9 Dec 2016 07:46:53 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from conuserg-11.nifty.com (conuserg-11.nifty.com [210.131.2.78]) by theia.denx.de (Postfix) with ESMTPS id 16D94A757A for ; Fri, 9 Dec 2016 07:46:50 +0100 (CET) Received: from pug.jp.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-11.nifty.com with ESMTP id uB96kg4G029503; Fri, 9 Dec 2016 15:46:43 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-11.nifty.com uB96kg4G029503 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1481266003; bh=1ago0HWzoxiQLBHxVtFrsUCcwaKXA9z5W5D16Feo4AQ=; h=From:To:Cc:Subject:Date:From; b=BoXxr9QS/gE87LV6A21XQm/2Py6QHmwkQE+hPd16ieukDJOedUuFdJnw7g5rCptAV Z5jeRLa9xtSYw127jaSSHQszUoFmxU58qYa5C1n8OhemYaNFRJcGl9suHg5fpV/XGb u2p9+TZvLCqgQgx5w9HWVx7HaO+QbMRFzlOSd0MJFb/PEo72Bg3x1QgigTUeYqv+Nv /EYLgkQoHz8mUnTz9OnY0fN0Hhy7gp3zxEapRKlM71ufd+ZbO6XV9/FYBI5XDeivSO U0z6G038uF8fJsMOXNNMSnYC3e0oIotwDOEjBpzfq7jx3g/8jN70FsiN+h/9TaR1bQ e5hmxaZJef/7A== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Fri, 9 Dec 2016 15:46:39 +0900 Message-Id: <1481265999-23626-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 Subject: [U-Boot] [PATCH] mmc: sdhci-cadence: add Cadence SD4HC support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add a driver for the Cadence SD4HC SD/SDIO/eMMC Controller. Signed-off-by: Masahiro Yamada --- - This is a counterpart of the Linux driver, which has been merged in the MMC subsystem: (commit ff6af28fa in linux-next) The DT binding for this driver should be referred in the kernel tree. - This will be applied cleanly after my SDHCI Kconfig moves: http://patchwork.ozlabs.org/patch/703578/ Until then, please review. drivers/mmc/Kconfig | 13 +++++ drivers/mmc/Makefile | 1 + drivers/mmc/sdhci-cadence.c | 125 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 139 insertions(+) create mode 100644 drivers/mmc/sdhci-cadence.c -- 2.7.4 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 12df3cf..9ca2f98 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -159,6 +159,19 @@ config MMC_SDHCI_BCM2835 If unsure, say N. +config MMC_SDHCI_CADENCE + bool "SDHCI support for the Cadence SD/SDIO/eMMC controller" + depends on MMC_SDHCI + depends on DM_MMC_OPS + depends on BLK + depends on OF_CONTROL + help + This selects the Cadence SD/SDIO/eMMC driver. + + If you have a controller with this interface, say Y or M here. + + If unsure, say N. + config MMC_SDHCI_KONA bool "SDHCI support on Broadcom KONA platform" depends on MMC_SDHCI diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 2b136ea..a543188 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -64,6 +64,7 @@ obj-$(CONFIG_MSM_SDHCI) += msm_sdhci.o # SDHCI obj-$(CONFIG_MMC_SDHCI) += sdhci.o obj-$(CONFIG_MMC_SDHCI_BCM2835) += bcm2835_sdhci.o +obj-$(CONFIG_MMC_SDHCI_CADENCE) += sdhci-cadence.o obj-$(CONFIG_MMC_SDHCI_KONA) += kona_sdhci.o obj-$(CONFIG_MMC_SDHCI_MV) += mv_sdhci.o obj-$(CONFIG_MMC_SDHCI_S5P) += s5p_sdhci.o diff --git a/drivers/mmc/sdhci-cadence.c b/drivers/mmc/sdhci-cadence.c new file mode 100644 index 0000000..1a59a5d --- /dev/null +++ b/drivers/mmc/sdhci-cadence.c @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +/* HRS - Host Register Set (specific to Cadence) */ +#define SDHCI_CDNS_HRS04 0x10 /* PHY access port */ +#define SDHCI_CDNS_HRS04_ACK BIT(26) +#define SDHCI_CDNS_HRS04_RD BIT(25) +#define SDHCI_CDNS_HRS04_WR BIT(24) +#define SDHCI_CDNS_HRS04_RDATA_SHIFT 12 +#define SDHCI_CDNS_HRS04_WDATA_SHIFT 8 +#define SDHCI_CDNS_HRS04_ADDR_SHIFT 0 + +/* SRS - Slot Register Set (SDHCI-compatible) */ +#define SDHCI_CDNS_SRS_BASE 0x200 + +/* PHY */ +#define SDHCI_CDNS_PHY_DLY_SD_HS 0x00 +#define SDHCI_CDNS_PHY_DLY_SD_DEFAULT 0x01 +#define SDHCI_CDNS_PHY_DLY_UHS_SDR12 0x02 +#define SDHCI_CDNS_PHY_DLY_UHS_SDR25 0x03 +#define SDHCI_CDNS_PHY_DLY_UHS_SDR50 0x04 +#define SDHCI_CDNS_PHY_DLY_UHS_DDR50 0x05 +#define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06 +#define SDHCI_CDNS_PHY_DLY_EMMC_SDR 0x07 +#define SDHCI_CDNS_PHY_DLY_EMMC_DDR 0x08 + +struct sdhci_cdns_plat { + struct mmc_config cfg; + struct mmc mmc; + void __iomem *hrs_addr; +}; + +static void sdhci_cdns_write_phy_reg(struct sdhci_cdns_plat *plat, + u8 addr, u8 data) +{ + void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS04; + u32 tmp; + + tmp = (data << SDHCI_CDNS_HRS04_WDATA_SHIFT) | + (addr << SDHCI_CDNS_HRS04_ADDR_SHIFT); + writel(tmp, reg); + + tmp |= SDHCI_CDNS_HRS04_WR; + writel(tmp, reg); + + tmp &= ~SDHCI_CDNS_HRS04_WR; + writel(tmp, reg); +} + +static void sdhci_cdns_phy_init(struct sdhci_cdns_plat *plat) +{ + sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_SD_HS, 4); + sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_SD_DEFAULT, 4); + sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_EMMC_LEGACY, 9); + sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_EMMC_SDR, 2); + sdhci_cdns_write_phy_reg(plat, SDHCI_CDNS_PHY_DLY_EMMC_DDR, 3); +} + +static int sdhci_cdns_bind(struct udevice *dev) +{ + struct sdhci_cdns_plat *plat = dev_get_platdata(dev); + + return sdhci_bind(dev, &plat->mmc, &plat->cfg); +} + +static int sdhci_cdns_probe(struct udevice *dev) +{ + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct sdhci_cdns_plat *plat = dev_get_platdata(dev); + struct sdhci_host *host = dev_get_priv(dev); + fdt_addr_t base; + int ret; + + base = dev_get_addr(dev); + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->hrs_addr = devm_ioremap(dev, base, SZ_1K); + if (!plat->hrs_addr) + return -ENOMEM; + + host->name = dev->name; + host->ioaddr = plat->hrs_addr + SDHCI_CDNS_SRS_BASE; + host->version = SDHCI_SPEC_300; + host->quirks |= SDHCI_QUIRK_WAIT_SEND_CMD; + + sdhci_cdns_phy_init(plat); + + ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0); + if (ret) + return ret; + + upriv->mmc = &plat->mmc; + host->mmc = &plat->mmc; + host->mmc->priv = host; + + return sdhci_probe(dev); +} + +static const struct udevice_id sdhci_cdns_match[] = { + { .compatible = "cdns,sd4hc" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(sdhci_cdns) = { + .name = "sdhci-cdns", + .id = UCLASS_MMC, + .of_match = sdhci_cdns_match, + .bind = sdhci_cdns_bind, + .probe = sdhci_cdns_probe, + .priv_auto_alloc_size = sizeof(struct sdhci_host), + .platdata_auto_alloc_size = sizeof(struct sdhci_cdns_plat), + .ops = &sdhci_ops, +};