From patchwork Tue Jan 10 04:32:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 90620 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp424804qgi; Mon, 9 Jan 2017 20:33:43 -0800 (PST) X-Received: by 10.223.138.9 with SMTP id w9mr529933wrw.50.1484022823601; Mon, 09 Jan 2017 20:33:43 -0800 (PST) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id kk10si559369wjc.3.2017.01.09.20.33.43; Mon, 09 Jan 2017 20:33:43 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7D0CCB38DF; Tue, 10 Jan 2017 05:33:25 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id RIZpgefspJeq; Tue, 10 Jan 2017 05:33:25 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4698AA7676; Tue, 10 Jan 2017 05:33:13 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B35DBA75F5 for ; Tue, 10 Jan 2017 05:32:46 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id KUCkNeiWggX1 for ; Tue, 10 Jan 2017 05:32:46 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from conuserg-10.nifty.com (conuserg-10.nifty.com [210.131.2.77]) by theia.denx.de (Postfix) with ESMTPS id 116D2B389A for ; Tue, 10 Jan 2017 05:32:41 +0100 (CET) Received: from pug.jp.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-10.nifty.com with ESMTP id v0A4WHbe027645; Tue, 10 Jan 2017 13:32:18 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-10.nifty.com v0A4WHbe027645 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1484022738; bh=F7KfGbnEEWuD3KquqDqLiS1dwDhUoiR0IVKa7thiBhY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UDkrdISqHvb7toQiFVRfSNsJZSEhD/gGgGBT7AvnM36uGm0UMQQM89Je45ZVsoht0 zB59/ZbSAgyerHEvKcoRxb+mjv5LOuJS74iRFIi0S1fCh1kZE+L65tnJdiWZxlPgDI 4FOns2wx8lrK211YJp9C7OUhoRd+tp32uMeb6HCFEQARD67xm+YkO4mzxyDS8ZwikO 4P7XVGAOKykm2pWsZzoJ/YRctGN3RVPv6TAb1XHqKijIIXY3bjkjbaeMP6B9+dHsZr eu9VYB9FNn+DJiEsmos5/PPzLe4NRN9CEeUzcjnVvtqUkXeczY44oz30br6VvrRb62 DChIA41ecaFgw== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Tue, 10 Jan 2017 13:32:02 +0900 Message-Id: <1484022728-9340-2-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1484022728-9340-1-git-send-email-yamada.masahiro@socionext.com> References: <1484022728-9340-1-git-send-email-yamada.masahiro@socionext.com> Cc: Marek Vasut , Albert Aribaud Subject: [U-Boot] [PATCH v2 1/7] ARM: socfpga: remove unused CONFIG option and cleanup README.socfpga X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH is defined in the socfpga_common.h, but not referenced at all. Remove. Also, clean-up the README.socfpga. CONFIG_MMC should not be defined in the header since it was moved to Kconfig by commit c27269953b94 ("mmc: complete unfinished move of CONFIG_MMC"). I see no grep hit for the others. Signed-off-by: Masahiro Yamada Reviewed-by: Marek Vasut --- Changes in v2: None doc/README.socfpga | 26 -------------------------- include/configs/socfpga_common.h | 1 - 2 files changed, 27 deletions(-) -- 2.7.4 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/doc/README.socfpga b/doc/README.socfpga index cfcbbfe..92942c9 100644 --- a/doc/README.socfpga +++ b/doc/README.socfpga @@ -14,12 +14,6 @@ socfpga_dw_mmc Here are macro and detailed configuration required to enable DesignWare SDMMC controller support within SOCFPGA -#define CONFIG_MMC --> To enable the SD MMC framework support - -#define CONFIG_SDMMC_BASE (SOCFPGA_SDMMC_ADDRESS) --> The base address of CSR register for DesignWare SDMMC controller - #define CONFIG_GENERIC_MMC -> Enable the generic MMC driver @@ -31,23 +25,3 @@ controller support within SOCFPGA #define CONFIG_SOCFPGA_DWMMC -> Enable the SOCFPGA specific driver for DesignWare SDMMC controller - -#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 --> The FIFO depth for SOCFPGA DesignWare SDMMC controller - -#define CONFIG_SOCFPGA_DWMMC_DRVSEL 3 --> Phase-shifted clock of sdmmc_clk for controller to drive command and data to -the card to meet hold time requirements. SD clock is running at 50MHz and -drvsel is set to shift 135 degrees (3 * 45 degrees). With that, the hold time -is 135 / 360 * 20ns = 7.5ns. - -#define CONFIG_SOCFPGA_DWMMC_SMPSEL 0 --> Phase-shifted clock of sdmmc_clk used to sample the command and data from -the card - -#define CONFIG_SOCFPGA_DWMMC_BUS_WIDTH 4 --> Bus width of data line which either 1, 4 or 8 and based on board routing. - -#define CONFIG_SOCFPGA_DWMMC_BUS_HZ 50000000 --> The clock rate to controller. Do note the controller have a wrapper which -divide the clock from PLL by 4. diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 31f1338..dda1159 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -146,7 +146,6 @@ #define CONFIG_GENERIC_MMC #define CONFIG_DWMMC #define CONFIG_SOCFPGA_DWMMC -#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 /* FIXME */ /* using smaller max blk cnt to avoid flooding the limited stack we have */ #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */