From patchwork Mon Mar 13 13:04:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 95220 Delivered-To: patch@linaro.org Received: by 10.140.82.71 with SMTP id g65csp1164718qgd; Mon, 13 Mar 2017 06:10:40 -0700 (PDT) X-Received: by 10.28.18.134 with SMTP id 128mr9497062wms.53.1489410639988; Mon, 13 Mar 2017 06:10:39 -0700 (PDT) Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id 18si10836274wms.61.2017.03.13.06.10.39; Mon, 13 Mar 2017 06:10:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 80400C21C81; Mon, 13 Mar 2017 13:08:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D4F60C21C66; Mon, 13 Mar 2017 13:08:45 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 2DF90C21C62; Mon, 13 Mar 2017 13:06:37 +0000 (UTC) Received: from fllnx209.ext.ti.com (fllnx209.ext.ti.com [198.47.19.16]) by lists.denx.de (Postfix) with ESMTPS id 88836C21C66 for ; Mon, 13 Mar 2017 13:06:33 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v2DD4sLN006709; Mon, 13 Mar 2017 08:04:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1489410294; bh=0SRrBXDCuxbeKuNan1UTkfd5eGTWz++KMD3by6OiHxA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=DIrE+GdSDbmQeRYRWHRdyBdK8ZDbWQguHk+VQjncwzS2mcCVCTkKOX8gx1ZRew1O7 wq4iBO+4y6RvQEgcdeqqWai4Z/PjhT7G+DuVYGRZ2d/ku42IYG8vuDk4H2L/Hh3gP4 semLrh2kOgcwVDorNk28FnBjxBSIG2TAjMjwjPNE= Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2DD4nRW031143; Mon, 13 Mar 2017 08:04:49 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Mon, 13 Mar 2017 08:04:48 -0500 Received: from lta0400828d.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2DD4YjP003968; Mon, 13 Mar 2017 08:04:47 -0500 From: Roger Quadros To: Date: Mon, 13 Mar 2017 15:04:29 +0200 Message-ID: <1489410273-10159-7-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1489410273-10159-1-git-send-email-rogerq@ti.com> References: <1489410273-10159-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de Subject: [U-Boot] [u-boot PATCH v4 06/10] board: ti: am571x-idk: Update pinmux for ICSS2 Ethernet X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Use the same convention that was used for ICSS1 Ethernet - If pin is output, set as PIN_OUTPUT - If pin is input and external pull resistor present set as PIN_INPUT - If pin is input and external pull resistor absent, set pull to same as that of the external PHY's internall pull. Signed-off-by: Roger Quadros Reviewed-by: Tom Rini Reviewed-by: Lokesh Vutla --- board/ti/am57xx/mux_data.h | 62 +++++++++++++++++++++++----------------------- 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/board/ti/am57xx/mux_data.h b/board/ti/am57xx/mux_data.h index ff0e517..5485212 100644 --- a/board/ti/am57xx/mux_data.h +++ b/board/ti/am57xx/mux_data.h @@ -586,46 +586,46 @@ const struct pad_conf_entry core_padconf_array_essential_am571x_idk[] = { {GPIO6_14, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_14.gpio6_14 */ {GPIO6_15, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_15.gpio6_15 */ {GPIO6_16, (M14 | PIN_INPUT_PULLDOWN)}, /* gpio6_16.gpio6_16 */ - {XREF_CLK0, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk0.pr2_mii1_col */ - {XREF_CLK1, (M11 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.pr2_mii1_crs */ + {XREF_CLK0, (M11 | PIN_INPUT)}, /* xref_clk0.pr2_mii1_col */ + {XREF_CLK1, (M11 | PIN_INPUT_PULLUP)}, /* xref_clk1.pr2_mii1_crs */ {XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.gpio6_19 */ {XREF_CLK3, (M15 | PIN_INPUT_PULLDOWN)}, /* xref_clk3.Driveroff */ {MCASP1_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_aclkx.pr2_mdio_mdclk */ {MCASP1_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_fsx.pr2_mdio_data */ {MCASP1_ACLKR, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkr.gpio5_0 */ {MCASP1_FSR, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_fsr.gpio5_1 */ - {MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.pr2_mii0_rxer */ - {MCASP1_AXR1, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr1.pr2_mii_mt0_clk */ + {MCASP1_AXR0, (M11 | PIN_INPUT_PULLUP)}, /* mcasp1_axr0.pr2_mii0_rxer */ + {MCASP1_AXR1, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr1.pr2_mii_mt0_clk */ {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */ {MCASP1_AXR3, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_axr3.gpio5_5 */ {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */ {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */ {MCASP1_AXR6, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_axr6.gpio5_8 */ {MCASP1_AXR7, (M14 | PIN_INPUT_PULLUP)}, /* mcasp1_axr7.gpio5_9 */ - {MCASP1_AXR8, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr8.pr2_mii0_txen */ - {MCASP1_AXR9, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr9.pr2_mii0_txd3 */ - {MCASP1_AXR10, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr10.pr2_mii0_txd2 */ - {MCASP1_AXR11, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr11.pr2_mii0_txd1 */ - {MCASP1_AXR12, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr12.pr2_mii0_txd0 */ - {MCASP1_AXR13, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.pr2_mii_mr0_clk */ - {MCASP1_AXR14, (M11 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* mcasp1_axr14.pr2_mii0_rxdv */ - {MCASP1_AXR15, (M11 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.pr2_mii0_rxd3 */ - {MCASP2_ACLKX, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_aclkx.pr2_mii0_rxd2 */ - {MCASP2_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_fsx.pr2_mii0_rxd1 */ + {MCASP1_AXR8, (M11 | PIN_OUTPUT)}, /* mcasp1_axr8.pr2_mii0_txen */ + {MCASP1_AXR9, (M11 | PIN_OUTPUT)}, /* mcasp1_axr9.pr2_mii0_txd3 */ + {MCASP1_AXR10, (M11 | PIN_OUTPUT)}, /* mcasp1_axr10.pr2_mii0_txd2 */ + {MCASP1_AXR11, (M11 | PIN_OUTPUT)}, /* mcasp1_axr11.pr2_mii0_txd1 */ + {MCASP1_AXR12, (M11 | PIN_OUTPUT)}, /* mcasp1_axr12.pr2_mii0_txd0 */ + {MCASP1_AXR13, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr13.pr2_mii_mr0_clk */ + {MCASP1_AXR14, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr14.pr2_mii0_rxdv */ + {MCASP1_AXR15, (M11 | PIN_INPUT)}, /* mcasp1_axr15.pr2_mii0_rxd3 */ + {MCASP2_ACLKX, (M11 | PIN_INPUT)}, /* mcasp2_aclkx.pr2_mii0_rxd2 */ + {MCASP2_FSX, (M11 | PIN_INPUT)}, /* mcasp2_fsx.pr2_mii0_rxd1 */ {MCASP2_ACLKR, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.Driveroff */ {MCASP2_FSR, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp2_fsr.Driveroff */ {MCASP2_AXR0, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr0.Driveroff */ {MCASP2_AXR1, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr1.Driveroff */ - {MCASP2_AXR2, (M11 | PIN_INPUT_SLEW)}, /* mcasp2_axr2.pr2_mii0_rxd0 */ - {MCASP2_AXR3, (M11 | PIN_INPUT_PULLDOWN | SLEWCONTROL)}, /* mcasp2_axr3.pr2_mii0_rxlink */ + {MCASP2_AXR2, (M11 | PIN_INPUT)}, /* mcasp2_axr2.pr2_mii0_rxd0 */ + {MCASP2_AXR3, (M11 | PIN_INPUT)}, /* mcasp2_axr3.pr2_mii0_rxlink */ {MCASP2_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr4.gpio1_4 */ {MCASP2_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr5.gpio6_7 */ {MCASP2_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr6.gpio2_29 */ {MCASP2_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr7.gpio1_5 */ - {MCASP3_ACLKX, (M11 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.pr2_mii0_crs */ - {MCASP3_FSX, (M11 | PIN_INPUT_SLEW)}, /* mcasp3_fsx.pr2_mii0_col */ - {MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr0.pr2_mii1_rxer */ - {MCASP3_AXR1, (M11 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp3_axr1.pr2_mii1_rxlink */ + {MCASP3_ACLKX, (M11 | PIN_INPUT_PULLUP)}, /* mcasp3_aclkx.pr2_mii0_crs */ + {MCASP3_FSX, (M11 | PIN_INPUT)}, /* mcasp3_fsx.pr2_mii0_col */ + {MCASP3_AXR0, (M11 | PIN_INPUT_PULLUP)}, /* mcasp3_axr0.pr2_mii1_rxer */ + {MCASP3_AXR1, (M11 | PIN_INPUT)}, /* mcasp3_axr1.pr2_mii1_rxlink */ {MCASP4_ACLKX, (M2 | PIN_INPUT_PULLDOWN)}, /* mcasp4_aclkx.spi3_sclk */ {MCASP4_FSX, (M2 | PIN_INPUT_PULLDOWN)}, /* mcasp4_fsx.spi3_d1 */ {MCASP4_AXR0, (M15 | PIN_INPUT_PULLDOWN)}, /* mcasp4_axr0.Driveroff */ @@ -642,18 +642,18 @@ const struct pad_conf_entry core_padconf_array_essential_am571x_idk[] = { {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */ {MMC1_SDCD, (M14 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.gpio6_27 */ {MMC1_SDWP, (M0 | PIN_OUTPUT)}, /* mmc1_sdwp.mmc1_sdwp */ - {GPIO6_10, (M11 | PIN_INPUT_PULLUP)}, /* gpio6_10.pr2_mii_mt1_clk */ - {GPIO6_11, (M11 | PIN_INPUT_PULLUP)}, /* gpio6_11.pr2_mii1_txen */ - {MMC3_CLK, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_clk.pr2_mii1_txd3 */ - {MMC3_CMD, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_cmd.pr2_mii1_txd2 */ - {MMC3_DAT0, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat0.pr2_mii1_txd1 */ - {MMC3_DAT1, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat1.pr2_mii1_txd0 */ - {MMC3_DAT2, (M11 | PIN_INPUT_PULLUP)}, /* mmc3_dat2.pr2_mii_mr1_clk */ + {GPIO6_10, (M11 | PIN_INPUT_PULLDOWN)}, /* gpio6_10.pr2_mii_mt1_clk */ + {GPIO6_11, (M11 | PIN_OUTPUT)}, /* gpio6_11.pr2_mii1_txen */ + {MMC3_CLK, (M11 | PIN_OUTPUT)}, /* mmc3_clk.pr2_mii1_txd3 */ + {MMC3_CMD, (M11 | PIN_OUTPUT)}, /* mmc3_cmd.pr2_mii1_txd2 */ + {MMC3_DAT0, (M11 | PIN_OUTPUT)}, /* mmc3_dat0.pr2_mii1_txd1 */ + {MMC3_DAT1, (M11 | PIN_OUTPUT)}, /* mmc3_dat1.pr2_mii1_txd0 */ + {MMC3_DAT2, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat2.pr2_mii_mr1_clk */ {MMC3_DAT3, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat3.pr2_mii1_rxdv */ - {MMC3_DAT4, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat4.pr2_mii1_rxd3 */ - {MMC3_DAT5, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat5.pr2_mii1_rxd2 */ - {MMC3_DAT6, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat6.pr2_mii1_rxd1 */ - {MMC3_DAT7, (M11 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat7.pr2_mii1_rxd0 */ + {MMC3_DAT4, (M11 | PIN_INPUT)}, /* mmc3_dat4.pr2_mii1_rxd3 */ + {MMC3_DAT5, (M11 | PIN_INPUT)}, /* mmc3_dat5.pr2_mii1_rxd2 */ + {MMC3_DAT6, (M11 | PIN_INPUT)}, /* mmc3_dat6.pr2_mii1_rxd1 */ + {MMC3_DAT7, (M11 | PIN_INPUT)}, /* mmc3_dat7.pr2_mii1_rxd0 */ {SPI1_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.gpio7_7 */ {SPI1_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.gpio7_8 */ {SPI1_D0, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.gpio7_9 */