From patchwork Fri Aug 25 16:12:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 111039 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp1240938qge; Fri, 25 Aug 2017 09:14:08 -0700 (PDT) X-Received: by 10.80.140.240 with SMTP id r45mr9675901edr.123.1503677648511; Fri, 25 Aug 2017 09:14:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1503677648; cv=none; d=google.com; s=arc-20160816; b=Zy75UMTe1htVbhhdB4/NAuvYlc9wTlxsXIkzDfJGdwalm/RYRbBVvVAHGB8vH2/HeV 1lfKDztQl6fNslYmqpKHn2EgrXc0mqIUPMYvXz47jFQzCGfVaPJZBIzKncUTzn7CU9bs igiScJ1ImVYKdGxFBJ4vkcdFGI8fNzAAWqP0iyQipcj3g+XKyibWLNuMKOnYOqmX/AjW 2qOAaYsxdjrd2O23rArBtufmX6ye/fZcduh3PL19nQCi+IFOTdjMgK3IK17wvifiZHhI 50efXlY8n+8ODK9coioT/vV7BUnIysdVh6Mb3UiNxNDlLFAN9XZG1IiKavljOVt5J0c9 ld2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature:dkim-filter:arc-authentication-results; bh=VtEZgBchXbxR2E0oUsSt1ylQim9vEgtAhSyUXhvEiCE=; b=GunJ1zcqBd9nScR02zAnGC5KjeDUn1i3Pwh8HVyNh6IDxw2k7y+NvoaECgHYzp4MaQ 4ixw2KyfIOmyFWFdQgRjuQUl7rLYPHOzlNDIh/dmuvsAz111pMrYGlUKL2SvweP2stR+ OJpwH3iOBjBF37ms1vJFp3C1E0UL2/c5e2z8daMkZ9C829GQbsgn/WRJgDCktqynywO3 Ev27SZQbV6azj0PQnQiPyV77tomB0ykw402wsLksveP+UM7sALdUA6lOUG+UlrQ3DX59 o+rduGp6V4R/3GwDZ8F+2onpSHjFigI+jdO9zMY4yCAATPCnlznz2tGTkF1oSM6SH6IA 8v1A== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=n9G0OZWf; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id 61si6082630edc.232.2017.08.25.09.14.08; Fri, 25 Aug 2017 09:14:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=n9G0OZWf; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id F3669C21F84; Fri, 25 Aug 2017 16:13:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 793A1C21F70; Fri, 25 Aug 2017 16:13:14 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 41637C21F64; Fri, 25 Aug 2017 16:13:09 +0000 (UTC) Received: from conuserg-09.nifty.com (conuserg-09.nifty.com [210.131.2.76]) by lists.denx.de (Postfix) with ESMTPS id 64F74C21F6B for ; Fri, 25 Aug 2017 16:13:08 +0000 (UTC) Received: from grover.sesame (FL1-122-131-185-176.osk.mesh.ad.jp [122.131.185.176]) (authenticated) by conuserg-09.nifty.com with ESMTP id v7PGCg5q016083; Sat, 26 Aug 2017 01:12:43 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-09.nifty.com v7PGCg5q016083 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1503677564; bh=cAiWHZs7RG5CRnB6dHM44EH/AtwgR7dNXK6YT1Rbhms=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=n9G0OZWfwQ6ltZ3ST6qVwA8AkqYdFmw9iAjQzu03CHCeDDsw2Y+QYnkYRJvtGzak8 bwYSPFve5/y7zAWeZt7KrL7J+gGFSjWl05Z6EJ2HbN3r469aGppxQYt8bDBGg8cTn2 UITJ3KtCAJQj0NkhFovyZINRpfx0xEemOY19MczhoxX4s9r6ZhwP/o0Ooq8H5sKpPd YkqOnfAXgeVCWakhISSMJwNrCj1A2S9mdaF9/LpKYtCH/U9oAepTD2a17BUEW4KYHn csWXFogTedsxRDaLE9Ejw8TPkWAeV0GTBvhPeVjAj0onmFlW+7YOZJS5/1Zwo39NtK R4aEsRy2cz9vw== X-Nifty-SrcIP: [122.131.185.176] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Sat, 26 Aug 2017 01:12:31 +0900 Message-Id: <1503677551-5085-3-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503677551-5085-1-git-send-email-yamada.masahiro@socionext.com> References: <1503677551-5085-1-git-send-email-yamada.masahiro@socionext.com> Cc: Scott Wood , Scott Wood Subject: [U-Boot] [PATCH 2/2] mtd: nand: denali_dt: add a DT driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" A patch for NAND uclass support was proposed about half a year: https://patchwork.ozlabs.org/patch/722282/ It was not merged and I do not see on-going work for this. Without DM-based probing, we need to set up pinctrl etc. in an ad-hoc way and give lots of crappy CONFIG options for base addresses and properties, which are supposed to be specified by DT. This is painful. This commit just provides a probe hook to retrieve "reg" from DT and allocate private data in a DM manner. This DT driver is not essentially a NAND driver, in fact it is (ab)using UCLASS_MISC. Once UCLASS_NAND is supported, it would be possible to migrate to it. Signed-off-by: Masahiro Yamada --- drivers/mtd/nand/Kconfig | 7 +++++ drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/denali.c | 4 ++- drivers/mtd/nand/denali.h | 2 ++ drivers/mtd/nand/denali_dt.c | 67 ++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 80 insertions(+), 1 deletion(-) create mode 100644 drivers/mtd/nand/denali_dt.c diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 71d678fc66b5..85b26d608851 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -16,6 +16,13 @@ config NAND_DENALI help Enable support for the Denali NAND controller. +config NAND_DENALI_DT + bool "Support Denali NAND controller as a DT device" + depends on NAND_DENALI && OF_CONTROL && DM + help + Enable the driver for NAND flash on platforms using a Denali NAND + controller as a DT device. + config SYS_NAND_DENALI_64BIT bool "Use 64-bit variant of Denali NAND controller" depends on NAND_DENALI diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index c3d4a996f37f..9f7d9d6ff7ae 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o obj-$(CONFIG_NAND_ARASAN) += arasan_nfc.o obj-$(CONFIG_NAND_DAVINCI) += davinci_nand.o obj-$(CONFIG_NAND_DENALI) += denali.o +obj-$(CONFIG_NAND_DENALI_DT) += denali_dt.o obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o obj-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 18280b0b2fe8..47cf37d1d9b7 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -1175,7 +1175,7 @@ static void denali_hw_init(struct denali_nand_info *denali) static struct nand_ecclayout nand_oob; -static int denali_init(struct denali_nand_info *denali) +int denali_init(struct denali_nand_info *denali) { struct mtd_info *mtd = nand_to_mtd(&denali->nand); int ret; @@ -1273,6 +1273,7 @@ fail: return ret; } +#ifndef CONFIG_NAND_DENALI_DT static int __board_nand_init(void) { struct denali_nand_info *denali; @@ -1296,3 +1297,4 @@ void board_nand_init(void) if (__board_nand_init() < 0) pr_warn("Failed to initialize Denali NAND controller.\n"); } +#endif diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h index 0e098bddf11d..694bce53a955 100644 --- a/drivers/mtd/nand/denali.h +++ b/drivers/mtd/nand/denali.h @@ -464,4 +464,6 @@ struct denali_nand_info { uint32_t max_banks; }; +int denali_init(struct denali_nand_info *denali); + #endif /* __DENALI_H__ */ diff --git a/drivers/mtd/nand/denali_dt.c b/drivers/mtd/nand/denali_dt.c new file mode 100644 index 000000000000..6a987c5b7880 --- /dev/null +++ b/drivers/mtd/nand/denali_dt.c @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2017 Socionext Inc. + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#include "denali.h" + +static const struct udevice_id denali_nand_dt_ids[] = { + { + .compatible = "altr,socfpga-denali-nand", + }, + { + .compatible = "socionext,uniphier-denali-nand-v5a", + }, + { + .compatible = "socionext,uniphier-denali-nand-v5b", + }, + { /* sentinel */ } +}; + +static int denali_dt_probe(struct udevice *dev) +{ + struct denali_nand_info *denali = dev_get_priv(dev); + struct resource res; + int ret; + + ret = dev_read_resource_byname(dev, "denali_reg", &res); + if (ret) + return ret; + + denali->flash_reg = devm_ioremap(dev, res.start, resource_size(&res)); + + ret = dev_read_resource_byname(dev, "nand_data", &res); + if (ret) + return ret; + + denali->flash_mem = devm_ioremap(dev, res.start, resource_size(&res)); + + return denali_init(denali); +} + +U_BOOT_DRIVER(denali_nand_dt) = { + .name = "denali-nand-dt", + .id = UCLASS_MISC, + .of_match = denali_nand_dt_ids, + .probe = denali_dt_probe, + .priv_auto_alloc_size = sizeof(struct denali_nand_info), +}; + +void board_nand_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(denali_nand_dt), + &dev); + if (ret) + printf("Failed to initialize Denali NAND controller.\n"); +}