From patchwork Fri Sep 15 12:43:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 112731 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp572943qgf; Fri, 15 Sep 2017 05:44:27 -0700 (PDT) X-Google-Smtp-Source: ADKCNb5jmd8FTlptpQaoCxlCp9IuxLgnzjq9GxX+Gw3IYMtQq/yIYRA6MLqrdzP+JzQeYXUKw9+b X-Received: by 10.80.165.23 with SMTP id y23mr13260976edb.155.1505479467873; Fri, 15 Sep 2017 05:44:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505479467; cv=none; d=google.com; s=arc-20160816; b=YESyQDmM/lQqYOHCbLdIJswRQ7cT5PwXJnjmylygTqnPJIdkkQj8HMWe17vw6RmH4/ 7JnlWEOWSsSqqbxSSbDL0gUf+vHNg1GcJ/4zLi9iJkvkQqshKGBaeBMy3lySqtDO6SId RlaMO36TNc0neEKNNxQBcOlApY4y2z9jdrNy+hQuqm1+F4OcUqcqKpHAUjatWCWh0a2B lkFP6yVaJR+Vk14fmfw9GbESY5SEZPdJgnfSZBFb+XWgELeC32HIf8lPPyNeWg3YJfmX pSSEB5f6hsMMvM+KV7N5zD5SWxCeVAQR5LTGPicDQBgVK2exFKfMLokizHOyu2qjkn0o K2gw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:message-id:date:to:from :dkim-signature:dkim-filter:arc-authentication-results; bh=VK92BPU0kO5zStQ9EBgUKtYme1oWb4v0K33WSY0HbFU=; b=fNRDDYPicM/o+CB4jp1FNEMKCqOv5lU91ZopbtHut4CFMQ1WCJwTBd2IX2/Hm12H1+ a5txjHN8X4vopBfPhPy4BtXUnNu7iSSGGgGQG0ZnbUGxkCAixm4bElppcqjKZU2x/Ps3 /dbYGu8zXCeqfggteYNyf0xJvOIbsPUvr1QJtKXSvg14goJn2hheHf9s+P8htFm50Tiz KiUMOWaNTyOKmzXWZKRcQRqInyULaALcwYdMC+CvwAKRW7OUbOXriF7igERBtHXFqGK5 Zp791vIqWQI2aw8FJuDlUv6R3xxr1W5mQxlZSG0azfsylflsoD7OUM6AA22/sz6eUzgS Efnw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=kTghOYMc; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id l63si1191850edl.104.2017.09.15.05.44.27; Fri, 15 Sep 2017 05:44:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=kTghOYMc; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 5B41EC2200C; Fri, 15 Sep 2017 12:44:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id BB94AC21F73; Fri, 15 Sep 2017 12:44:17 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8D36EC21FFB; Fri, 15 Sep 2017 12:44:04 +0000 (UTC) Received: from conuserg-11.nifty.com (conuserg-11.nifty.com [210.131.2.78]) by lists.denx.de (Postfix) with ESMTPS id CF907C22009 for ; Fri, 15 Sep 2017 12:43:59 +0000 (UTC) Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-11.nifty.com with ESMTP id v8FChYNu026429; Fri, 15 Sep 2017 21:43:35 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-11.nifty.com v8FChYNu026429 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1505479415; bh=yL45//VAwEq+A1bFOPG3gm96hfy8gxJagfgapCNmx9U=; h=From:To:Cc:Subject:Date:From; b=kTghOYMcUvv5/mFFbVYOth9XVowNb5vaXNc8l91sZMh8V7GJg6ObOC7MzD3bTjiEG rGWWRJIOO4Z9ekr0LHtOl8ut2W5L57tD8frYX2z/g/5USKZzvg6XhBDETgwEJ0THi1 lwxcKK2BXIOsGLMl5Nm54gV+VVPd7NcJzxfpq3WHywrvYVDygNJRCNAr85lbnJJopA cr+MUEpVebfvId93deShhr4RnqoL8LBSbZerOSJB35M0rbMbrfOB1KGqtb5J7nR1fA 7YKiv7x1Tyc7RbBbowSWc0X+kMU8HBEjIr8nXBPCJu2lEH3HwFrEC72flk41UC6eI+ qRTQhAxR78lSw== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Fri, 15 Sep 2017 21:43:19 +0900 Message-Id: <1505479402-17945-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 Cc: Scott Wood , Scott Wood Subject: [U-Boot] [PATCH 1/4] mtd: nand: denali: allow to override corrupted revision register X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The Denali IP does not update the revision register properly. Allow to override it with SoC data associated with compatible. Linux had already finished big surgery of this driver, but I need to prepare the NAND core before the full sync of the driver. For now, I am fixing the most fatal problem on UniPhier platform. Signed-off-by: Masahiro Yamada --- drivers/mtd/nand/denali.c | 27 +++++++++++++++------------ drivers/mtd/nand/denali.h | 7 +++++-- drivers/mtd/nand/denali_dt.c | 30 ++++++++++++++++++++++++++++++ 3 files changed, 50 insertions(+), 14 deletions(-) diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 47cf37d..54718f4 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include "denali.h" @@ -433,17 +433,13 @@ static void find_valid_banks(struct denali_nand_info *denali) */ static void detect_max_banks(struct denali_nand_info *denali) { - uint32_t features = readl(denali->flash_reg + FEATURES); - /* - * Read the revision register, so we can calculate the max_banks - * properly: the encoding changed from rev 5.0 to 5.1 - */ - u32 revision = MAKE_COMPARABLE_REVISION( - readl(denali->flash_reg + REVISION)); - if (revision < REVISION_5_1) - denali->max_banks = 2 << (features & FEATURES__N_BANKS); - else - denali->max_banks = 1 << (features & FEATURES__N_BANKS); + uint32_t features = ioread32(denali->flash_reg + FEATURES); + + denali->max_banks = 1 << (features & FEATURES__N_BANKS); + + /* the encoding changed from rev 5.0 to 5.1 */ + if (denali->revision < 0x0501) + denali->max_banks <<= 1; } static void detect_partition_feature(struct denali_nand_info *denali) @@ -1154,6 +1150,13 @@ static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, static void denali_hw_init(struct denali_nand_info *denali) { /* + * The REVISION register may not be reliable. Platforms are allowed to + * override it. + */ + if (!denali->revision) + denali->revision = swab16(ioread32(denali->flash_reg + REVISION)); + + /* * tell driver how many bit controller will skip before writing * ECC code in OOB. This is normally used for bad block marker */ diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h index 694bce5..08db488 100644 --- a/drivers/mtd/nand/denali.h +++ b/drivers/mtd/nand/denali.h @@ -166,8 +166,6 @@ #define REVISION 0x370 #define REVISION__VALUE 0xffff -#define MAKE_COMPARABLE_REVISION(x) swab16((x) & REVISION__VALUE) -#define REVISION_5_1 0x00000501 #define ONFI_DEVICE_FEATURES 0x380 #define ONFI_DEVICE_FEATURES__VALUE 0x003f @@ -462,8 +460,13 @@ struct denali_nand_info { uint32_t blksperchip; uint32_t bbtskipbytes; uint32_t max_banks; + unsigned int revision; + unsigned int caps; }; +#define DENALI_CAP_HW_ECC_FIXUP BIT(0) +#define DENALI_CAP_DMA_64BIT BIT(1) + int denali_init(struct denali_nand_info *denali); #endif /* __DENALI_H__ */ diff --git a/drivers/mtd/nand/denali_dt.c b/drivers/mtd/nand/denali_dt.c index 0a6155c..4afd679 100644 --- a/drivers/mtd/nand/denali_dt.c +++ b/drivers/mtd/nand/denali_dt.c @@ -12,15 +12,38 @@ #include "denali.h" +struct denali_dt_data { + unsigned int revision; + unsigned int caps; +}; + +static const struct denali_dt_data denali_socfpga_data = { + .caps = DENALI_CAP_HW_ECC_FIXUP, +}; + +static const struct denali_dt_data denali_uniphier_v5a_data = { + .caps = DENALI_CAP_HW_ECC_FIXUP | + DENALI_CAP_DMA_64BIT, +}; + +static const struct denali_dt_data denali_uniphier_v5b_data = { + .revision = 0x0501, + .caps = DENALI_CAP_HW_ECC_FIXUP | + DENALI_CAP_DMA_64BIT, +}; + static const struct udevice_id denali_nand_dt_ids[] = { { .compatible = "altr,socfpga-denali-nand", + .data = (unsigned long)&denali_socfpga_data, }, { .compatible = "socionext,uniphier-denali-nand-v5a", + .data = (unsigned long)&denali_uniphier_v5a_data, }, { .compatible = "socionext,uniphier-denali-nand-v5b", + .data = (unsigned long)&denali_uniphier_v5b_data, }, { /* sentinel */ } }; @@ -28,9 +51,16 @@ static const struct udevice_id denali_nand_dt_ids[] = { static int denali_dt_probe(struct udevice *dev) { struct denali_nand_info *denali = dev_get_priv(dev); + const struct denali_dt_data *data; struct resource res; int ret; + data = (void *)dev_get_driver_data(dev); + if (data) { + denali->revision = data->revision; + denali->caps = data->caps; + } + ret = dev_read_resource_byname(dev, "denali_reg", &res); if (ret) return ret;